Vertical GaN-on-Si membrane power transistors: Efficient power electronics for mass-market applications (VertiGaN)`

垂直硅基氮化镓薄膜功率晶体管：面向大众市场应用的高效电力电子器件 (VertiGaN)`

• 批准号: EP/X014924/1
• 负责人: Matthew Smith
• 金额: $ 41.89万
• 依托单位: University of Bristol
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2024
• 资助国家: 英国
• 起止时间: 2024 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FX014924%2F1
• 关键词: Vertical; GaN; Si; membrane; power

This project aims to realize transformative vertical gallium nitride-on-silicon (GaN-on-Si) transistors with breakdown voltage in excess of 1200 V. Power electronics is essential in applications including power distribution and transportation, with inefficiency of power electronic systems estimated to account for 20% of global carbon emissions. Furthermore, emerging low-carbon technologies, including electric vehicles and renewable energy generation, require power electronic devices with significant improvements over existing Si based solutions. GaN is a wide bandgap semiconductor alternative to Si, with superior power electronic material properties. Commercially-available lateral GaN transistors show good power performance, but are generally unsuitable for applications >1000 V due to high on resistance and large chip area. Vertical GaN transistors (where current flows into the plane of the chip, rather than along the surface) offer a step-increase in efficiency and power density over Si-based devices currently dominant in power electronics at voltages exceeding 1000 V. Large-scale commercialisation of vertical GaN devices is currently inhibited by the requirement for expensive and unsustainable GaN bulk substrates. Transfer to sustainable Si substrates as proposed here, with a cost reduction of >1000x, requires management of associated material defects, to be achieved in this work through of implementation of novel device structures and optimisation of material growth processes. Demonstration of vertical GaN on Si transistors with breakdown voltage of >1200 V (i.e. voltage at which device failure occurs), improved from <600 V in previous attempts, will enable exploitation of the outstanding GaN material properties in emerging mass market applications at >1000 V, unlocking new applications and enabling reduced carbon emissions in next-generation power electronic systems including electric vehicles and power distribution. Breakdown voltage in vertical GaN-on-Si transistors will be increased through improvement of material quality in the active device drift region. The novel structure will use an epitaxially-embedded n+GaN drain contact layer to facilitate a drain-recessed membrane device architecture, eliminating low-quality material from the active device region. In parallel, optimisation of epitaxial growth techniques will produce GaN-on-Si material with increased total thickness and a reduction in both dislocation density and background impurity levels. Drain-recessed GaN-on-Si membrane structures will then be integrated with finFET device topologies, shown to withstand operation voltages >1200 V in GaN-on-GaN, resulting in transistors with enhanced off-state blocking and on-state electron transport characteristics. The development workplan, in close collaboration and with strong support by industry, will enable both a thorough exploration of the underlying physics determining vertical breakdown in GaN-on-Si and improvements in device performance toward that required for large-scale commercialisation. Comprehensive failure analysis via reliability/stability testing and multiphysics modelling will provide further understanding of the GaN-on-Si material system and commercial potential.Technology demonstrators will be optimally positioned for integration with next-generation manufacturing chains and testing systems, ensuing maximum commercial impact. This will be achieved through regular consultation with the Project Steering Committee, consisting of UK-based manufacturers of power electronic materials, devices and systems, as well as academics and a prominent UK government policy influencer. The use of a Design Kit to promote the benefits of the technology to system designers and manufacturers will ensure maximum uptake and identification of additional application areas, toward achieving wide-scale use of GaN devices and an associated reduction in carbon emissions from inefficiency of power electronics.

该项目旨在实现击穿电压超过1200V的变革性垂直氮化镓(GaN-on-Si)晶体管。电力电子在配电和运输等应用中是必不可少的，电力电子系统的低效估计占全球碳排放的20%。此外，新兴的低碳技术，包括电动汽车和可再生能源发电，需要比现有的硅基解决方案有显著改进的电力电子器件。GaN是一种替代硅的宽禁带半导体材料，具有优异的电力电子材料性能。商业上可用的横向GaN晶体管具有良好的功率性能，但由于导通电阻高和芯片面积大，通常不适合&GT；1000V的应用。垂直GaN晶体管(电流流入芯片平面，而不是沿表面)在超过1000V的电压下，提供了比目前电力电子中占主导地位的硅基器件更高的效率和功率密度。目前，由于对昂贵且不可持续的GaN体基衬底的需求，垂直GaN器件的大规模商业化受到限制。这里提出的向可持续硅衬底转移，成本降低1000倍，需要通过实施新的器件结构和优化材料生长过程来实现对相关材料缺陷的管理。对击穿电压为&gt；1200 V(即发生器件故障时的电压)的垂直GaN on Si晶体管的演示(比之前的尝试中的&lt；600 V有所改进)，将能够在&gt；1000 V的新兴大众市场应用中利用出色的GaN材料特性，开启新的应用，并在包括电动汽车和配电在内的下一代电力电子系统中减少碳排放。通过改善有源器件漂移区的材料质量，可以提高垂直GaN-on-Si晶体管的击穿电压。这种新颖的结构将使用外延嵌入的n+GaN漏接触层来促进漏凹式薄膜器件架构，从而消除有源器件区域中的低质量材料。同时，外延生长技术的优化将产生总厚度增加、位错密度和背景杂质水平降低的GaN-on-Si材料。然后，漏凹式GaN-on-Si薄膜结构将与FinFET器件拓扑集成，可承受GaN-on-GaN中的操作电压&gt；1200V，从而产生具有增强的关态阻断和导通电子传输特性的晶体管。在密切合作和业界的大力支持下，开发工作计划将使人们能够彻底探索决定GaN-on-Si垂直击穿的潜在物理因素，并将器件性能提高到大规模商业化所需的水平。通过可靠性/稳定性测试和多物理模型进行的全面故障分析将进一步了解硅基GaN材料系统和商业潜力。技术示范者将处于与下一代制造链和测试系统集成的最佳位置，从而实现最大的商业影响。这将通过与项目指导委员会定期磋商来实现，该委员会由总部设在英国的电力电子材料、设备和系统制造商以及学者和一位著名的英国政府政策影响者组成。使用设计套件向系统设计者和制造商宣传该技术的好处，将确保最大限度地吸收和识别更多的应用领域，从而实现GaN器件的广泛使用，并相关地减少电力电子低效造成的碳排放。