SHF: Small: Mainstream Transactional Memory

标题：SHF: Small：主流事务性内存事务性内存（TM）是两个变革思想的结合：首先，如果程序员可以简单地指定代码中的哪些操作应该是原子的，而不指定如何使它们原子化，那么并行编程将更容易；其次，这种简单性可以通过一种推测性实现来支持——并且性能通常会得到改善——这种实现可以并行地执行原子块，并在这些块相互冲突时（且仅在这些块相互冲突时）退出并重试。经过多年的研究，TM现在正进入广泛的应用。硬件支持在商业上可以从IBM和Intel获得；软件支持是Haskell的标准，其他几种编程语言（尤其是c++）也在考虑中。赞助的研究通过关注(1)快速硬件事务的软件加速和(2)丰富软件事务的硬件加速来扩展事务性内存的技术状态。重点领域1中的智力优点包括基于编译器的技术，通过安全、自动地将经常冲突的操作移出事务，以及通过“流水线”执行来序列化冲突的剩余原因，从而提高投机成功率。重点领域2的智力优势包括对针对Haskell编程语言的STM运行时系统的增强，其中可以使用硬件支持来加速语义过于复杂而无法直接使用商业硬件实现的事务。更广泛的影响始于更容易地构建正确、高效的并行代码，这将允许所有技能水平的程序员更容易地编写代码。此外，这项工作将通过平滑过渡到无处不在的多线程来影响计算机科学和相关领域，从而通过下一代计算扩展性能改进。总之，这项工作将在学术界和工业界几乎所有由并行计算驱动的领域取得进展。

Title: SHF: Small: Mainstream Transactional MemoryTransactional Memory (TM) is the union of two transformative ideas: first, that parallel programming will be easier if programmers can simply specify which operations in their code should be atomic, without specifying how to make them atomic; second, that this simplicity can be supported -- and performance often improved -- by a speculative implementation that executes atomic blocks in parallel, and backs out and retries when -- and only when -- those blocks conflict with one another. After many years of research, TM is now entering widespread use. Hardware support is commercially available from both IBM and Intel; software support is standard in Haskell and under consideration in several other programming languages -- notably C++. The sponsored research extends the state of the art in transactional memory by focusing on (1) software acceleration of fast hardware transactions and (2) hardware acceleration of rich software transactions.The intellectual merits in focus area 1 comprise compiler-based techniques to increase speculation success rates, by safely and automatically moving commonly conflicting operations out of transactions, and by "pipelining" execution to serialize the remaining causes of conflict. The intellectual merits in focus area 2 comprise enhancements to the STM run-time system for the Haskell programming language, where hardware support can be used to accelerate transactions whose semantics are too complex to implement directly with commercial hardware. The broader impacts begin with easier construction of correct, efficient parallel code that will allow programmers of all skill levels to write that code more easily. Moreover, the work will impact computer science and allied fields by smoothing the transition to ubiquitous multithreading, thereby extending performance improvements through the next generation of computing. In summary, the work will lead to progress in almost any domain that is driven by parallel computing, across academia and industry.