SBIR Phase I: Integrated Nano-Electro-Mechanical Scanning Probes for Failure Analysis of the 10-Nanometer Node and Beyond

这个小型企业创新研究第一阶段项目将专注于开发一种用于半导体器件故障隔离和分析的多集成针尖扫描探头设备。潜在的激励因素来自于缺乏高分辨率和高灵敏度的测试设备，随着半导体行业将特征尺寸缩小到10纳米或更高，识别故障所需的测试设备。集成设备的成功开发和使用将使工程师能够了解这些高级节点上固态设备故障机制的根本原因。这种新的故障分析功能对下一代设备的商业影响将是深远的。半导体器件的小型化导致每个晶体管的成本在过去40年中下降了7个数量级，需要新的工艺和测量技术来继续这一趋势。晶体管尺寸的减小使高性能器件能够以更低的成本和更低的功耗实现。拟议的多针尖技术将使这些先进的节点高比例晶体管的开发成为可能，这些晶体管将形成下一代高性能电子设备的平台，如个人计算机、手机和医疗设备。该项目的智能优点是使用单片集成扫描探头，以便于将半导体故障分析扩展到特征尺寸为10纳米或更小的设备。至关重要的是，当应用于小于100纳米的结构时，传统的表征和测试方法越来越无效，这给工程师在研发、过程控制和故障分析方面带来了挑战。随着器件尺寸和操作裕度的减小，细微缺陷成为故障的日益突出的驱动因素，例如，薄栅氧化物中的工艺异常、与掺杂相关的衬底问题以及线宽变化。这些问题可能发生在传统扫描电子显微镜和基于光学的工具看不到的长度范围内，需要新的方法。建议的多个集成针尖设备利用强大的纳米机电能力，甚至可以扩展到10纳米以下。此外，纳米制造技术的成本效益，再加上传感结构的单片集成和尖端的定制，将能够实现稳健的大容量测试，这是半导体行业的关键需求。研究目标包括纳米级多集成针尖器件的制造、晶体管的原子力成像和晶体管的有源电学表征。预期的结果是使用多个集成针尖器件准确地描述晶体管的性能。

This Small Business Innovation Research Phase I project will focus on the development of a multiple integrated tip scanning probe device for use in semiconductor device failure isolation and analysis. The underlying motivating factor stems from a lack of testing equipment with high resolution and sensitivity necessary for identifying faults as the semiconductor industry shrinks feature sizes to 10 nanometers and beyond. Successful development and use of the integrated device will allow engineers to understand the root cause of failure mechanisms of solid state devices at these advanced nodes. The commercial impact of this new capability for failure analysis on next-generation devices will be profound. The miniaturization of semiconductor devices has led to a decrease in the cost per transistor of seven orders of magnitude in the last 40 years, and new process and measurement technologies are needed to continue this trend. The reduction of transistor size enables high performance devices at a lower cost and lower power. The proposed multiple tip technology will enable the development of these advanced-node highly scaled transistors that will form the platform for the next generation of high-performance electronic devices such as personal computers, cell phones, and healthcare equipment. The intellectual merit of this project is the use of monolithically integrated scanning probes to facilitate the extension of semiconductor failure analysis to devices with feature sizes of ten nanometers or less. Crucially, conventional characterization and test methods are increasingly ineffective when applied to structures smaller than 100 nanometers, causing challenges for engineers in research and development, process control and failure analysis. Subtle defects become increasingly prominent drivers of failure as device size and operating margins decrease, e.g., processing anomalies in thin gate oxides, substrate problems related to doping, and line width variations. These issues can occur at length scales invisible to traditional scanning electron microscopy and optical-based tools, requiring novel approaches. The proposed multiple integrated tip devices leverage powerful nano-electro-mechanical capabilities and scale well even below 10 nanometers. In addition, cost effectiveness of the nanofabrication techniques, combined with monolithic integration of sensing structures and tailoring of the tips would enable robust, high-volume testing, a key need for the semiconductor industry. Research objectives include the fabrication of nanoscale multiple integrated tip devices, atomic force imaging of transistors and active electrical characterization of transistors. The anticipated result is accurate electrical characterization of transistor performance using the multiple integrated tip device.