CAREER: Energy-Efficient and Energy-Proportional Silicon-Photonic Manycore Architectures

日益增长的能源需求使计算走上了一条不可持续的技术、经济和环境道路。不幸的是，很大一部分能源被浪费了，数据传输是能源消耗的主要贡献者之一。与此同时，随着计算需求的增长，现代微处理器越来越多地受到物理限制的限制，这阻碍了它们充分发挥潜力。面积、功率、散热、片外带宽和成品率限制将单芯片设计限制在相对较少的内核数量，超过这个数量，扩展变得不切实际。多芯片设计可以克服这些限制，但需要跨芯片互连，其带宽、延迟和能效特性远远超出传统电信号的范围。引入纳米光子互连，如本提案中所承诺的，可以满足这些要求，使系统摆脱单芯片设计的限制。在这项研究的背景下，严格的教育计划也被纳入研究议程，将研究与教育紧密联系起来，并加强少数群体和本科生对研究的参与。该项目利用与西北大学Searle卓越教学中心的现有合作，实施创新的教育方法，西北大学S社会科学面向公众的推广倡议，以及西北大学S STEM教育伙伴关系办公室开发K-12 STEM推广活动，其扩展潜力扩展到芝加哥大都市区的140多所学校，覆盖368名教师和30,000名学生。本研究的具体技术方面旨在为未来的多核开发可扩展、节能和能量比例的互联。为了实现这一愿景，这项研究试图了解并缓解硅光电子领域占主导地位的电力消费者的能源效率低下问题。该项目涉及一种交叉方法，将新材料、新兴设备和3D堆叠的开发与建筑和微建筑技术、存储系统、运行时环境和操作系统的研究相结合，以开发自适应技术，在不牺牲纳米光子互连的性能的情况下将能耗降至最低。这一总体努力的最终结果是设计了一个虚拟宏芯片，这是一种分散的多核设计，由硅-光子互连支持，可达到数千个核的规模，其性能和功率水平是传统技术无法实现的。

Increasing energy demands have put computing on an unsustainable technological, economic and environmental path. Unfortunately, a large fraction of this energy is wasted, with data transfers being one of the major contributors to energy consumption. At the same time, while the demand for computing grows, modern microprocessors are increasingly constrained by physical limitations, which prevent them from realizing their full potential. Area, power, thermal, off-chip bandwidth, and yield limitations constrain single-chip designs to a relatively small number of cores, beyond which scaling becomes impractical. Multi-chip designs can overcome these limitations, but require a cross-chip interconnect with bandwidth, latency, and energy efficiency characteristics well beyond the reach of conventional electrical signaling. Introduction of nano-photonic interconnects, as undertaken in this proposal, can meet these requirements and allow systems to break free of the limitations of single-chip designs. Within the context of this research, a rigorous educational plan is also integrated into the research agenda that strongly connects research to education, and enhances the participation of minorities and undergraduates in research. This project capitalizes on existing collaborations with the Searle Center for Teaching Excellence at Northwestern University to implement innovative educational approaches, Northwestern?s Science in Society outreach initiatives for the general public, and Northwestern?s Office of STEM Education Partnerships to develop K-12 STEM outreach activities with outreach potential extending to 140+ schools in the Chicago metropolitan area, reaching 368 teachers and 30,000 students.Specific technical aspects of this research aims to develop scalable, energy-efficient, and energy-proportional interconnects for future multicores. To achieve this vision, the research seeks to understand and mitigate the energy inefficiencies of the dominant power consumers in silicon-photonics. The project involves a cross-cutting approach to combine developments in novel materials, emerging devices, and 3D-stacking with research in architectural and micro-architectural techniques, memory systems, the runtime environment, and the operating system, to develop adaptive techniques that minimize the energy consumed by nano-photonic interconnects without sacrificing their performance. The overall effort culminates on the design of a virtual macro-chip, a disaggregated many-core design supported by a silicon-photonic interconnect that reaches scales of thousands of cores, at a performance and power level impossible to realize with conventional technology.