SBIR Phase I: Thin crystalline technologies for advanced power transistors

小型企业创新研究(SBIR)第一阶段项目的更广泛影响/商业潜力是使更小的充电器、功率因数转换器和开关能够应用于从植入式起搏器、移动电话、计算机等小型应用到汽车、机械等大型应用，再到船舶、机车、传统和可再生能源发电厂等超大型应用。虽然使用该技术开发的电源开关产品在该二期项目中的影响是广泛的，但这种薄晶体技术的使用可能会对所有现代半导体设备产生更广泛的影响，如LED、光伏、柔性CMOS和无源设备。这个小型企业创新研究(SBIR)第一阶段项目解决了功率MOSFET进一步扩展的挑战，功率MOSFET是我们在过去几十年见证的电子革命的关键组成部分之一。虽然晶体管的特征尺寸一直在不断缩小，但衬底厚度一直在增加。这些基板目前被机械地减薄，以最大限度地减少厚度增加对性能和外形因素的负面影响。延续这一趋势面临着巨大的挑战，这里提出的薄晶技术和设备架构可以在未来十年内以有利的成本结构继续扩展设备指标。这项工作将重点解决将其推向市场的以下具体技术挑战。(1)利用薄晶体技术开发具有改进开关特性的功率MOSFET(2)开发当前生产线上使用的大面积晶片的工艺技术(3)利用薄晶体剥离技术的金属化特性开发低形状因数封装(4)表征器件的性能并将其插入高容量去风险(5)为一系列可持续十年的产品制定路线图，以证明将该技术推向市场的重大制造投资是合理的。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to enable smaller chargers, power factor convertors and switches in applications ranging from small applications such as implanted pace-makers, mobile-phones, computer to large applications such as automobile, machinery to very large applications such as ships, locomotives, traditional and renewable energy power plants. While the impact of the power switching product to be developed using this technology in this phase II project is broad, the use of this thin crystalline technology can have even broader impact across all modern semiconductor devices such as LED, PV, flexible CMOS and passive devices. The project will potentially enable thin form-factor packages in this broad range of power electronics applications.This Small Business Innovation Research (SBIR) Phase I project addresses challenges to further scaling of power MOSFETs which are one of the key building blocks of the electronic revolution we have witnessed over the last few decades. While the feature size of transistors has been constantly shrinking, the substrate thickness has been increasing. These substrates are currently mechanically thinned to minimize the negative impact of this increased thickness on performance and form-factor. There are significant challenges to continue this trend and the thin crystalline technology and device architecture proposed here can enable continued scaling of device metrics over the next decade with favorable cost structures. This effort will focus on the following specific technical challenges to bring it to market. (1) Develop power MOSFETs with improved switching characteristics using the thin crystalline technology (2) Develop the process technology on large area wafers used in current production lines (3) Develop the low-form factor package using the metallization features of thin-crystalline exfoliated technology (4) Characterize the device for performance and insertion into high volume de-risk (5) Develop a roadmap for a family of products that is sustainable over a decade to justify significant manufacturing investment to bring this technology to market.