SHF: SMALL: Parallelization and Memory System Techniques for Heterogeneous Microprocessors

传统的离散GPU已经展示了相对于CPU的显著性能提升，但这些改进仅限于具有大规模并行性的简单代码。 最近，计算机制造商已经生产了异构微处理器，其中CPU和GPU集成在同一管芯上。 这样的处理器提供CPU和GPU之间的共享存储器，以及快速的CPU-GPU通信。 这些功能可能会加速新类型的计算，使GPU能够有效地执行更小的循环并支持更复杂的代码。 本项目研究利用异构微处理器的技术，并实现其效益。 如果成功，该项目将使大多数程序，而不仅仅是那些具有大量并行性的程序，能够利用GPU。 该项目还将为研究生和本科生提供有价值的培训，并改善研究生水平的课程。在研究方面，该项目将追求以下研究方向。 首先，它将创建一套展示复杂循环嵌套的基准测试程序，以展示异构微处理器的新功能。 其次，该项目还将为新的基准套件开发新的并行化方案。 并行化方案将同时将多个并行级别映射到CPU和GPU核心，以充分利用异构微处理器中的计算资源。 第三，将开发新的高速缓存一致性协议，有效地支持批量生产者-消费者通信，这种通信发生在细粒度计算从CPU迁移到GPU并返回时。 最后，自适应内存地址映射方案将研究利用DRAM页局部性的CPU访问和GPU访问的通道级并行。

Traditional discrete GPUs have demonstrated dramatic performance gains over CPUs, but the improvements have been limited to simpler codes with massive parallelism. Recently, computer manufacturers have been producing heterogeneous microprocessors in which a CPU and GPU are integrated on the same die. Such processors provide shared memory between the CPU and GPU, and fast CPU-GPU communication. These features potentially enable acceleration of new types of computations, allowing the GPU to gainfully execute smaller loops and to support more complex codes. This project investigates techniques for exploiting heterogeneous microprocessors and to realize their benefits. If successful, the project will enable most programs, not just those with massive parallelism, to utilize GPUs. The project will also provide valuable training to both graduate and undergraduate students, and improve graduate-level coursework.On the research side, the project will pursue the following research directions. First, it will create a suite of benchmarks exhibiting complex loop nests that demonstrate the new capabilities of heterogeneous microprocessors. Second, the project will also develop novel parallelization schemes for the new benchmark suite. The parallelization schemes will map multiple levels of parallelism to CPU and GPU cores simultaneously to fully utilize the compute resources in a heterogeneous microprocessor. Third, new cache coherence protocols will be developed that efficiently support the bulk producer-consumer communication that occurs as finer-grained computations migrate from CPU to GPU and back. And finally, adaptive memory address mapping schemes will be investigated that exploit DRAM page locality for CPU accesses and channel-level parallelism for GPU accesses.