SHF: Small: Developing and Applying Reuse Distance Analysis Techniques for Large-Scale Multicore Processors

今天，模拟是研究多核缓存层次结构的实际方法。 但是，由于涉及到组合设计空间，仿真的成本很高，特别是当多核处理器扩展到100个内核和100多MB的片上缓存时。 重用距离（RD）分析可以帮助架构师更有效地评估多核内存性能。 不幸的是，多核处理器中的局部性取决于每个线程的内存引用流如何交织。 对内存交错的依赖使得多核局部性配置文件依赖于架构，限制了它们分析不同配置的能力。然而，对于基于循环的并行程序，线程通常是对称的，并表现出类似的局部性特征。 这样的线程对称性使得多核RD分析易于处理：局部性配置文件相对于缓存容量缩放保持稳定，并随着核心数和问题大小缩放而系统地变化。本项目正在探索与基于循环的并行程序的多核RD分析相关的几个研究方向。 首先，它描述了对称线程的并发RD和每线程RD配置文件如何随处理器和问题扩展而变化。 第二，它正在开发预测这些剖面变化的技术。 简单的预测技术，如参考群体，以及更复杂的参数和非参数学习方法，正在研究中。 最后，它正在应用新的RD分析来探索大规模多核设计空间，确定良好的缓存层次结构组织。 它还使用RD分析来改进现有的内存性能增强技术，如多线程和局部优化。

Today, simulation is the de facto method for studying multicore cache hierarchies. But simulation is costly due to the combinatorial design spaces involved, especially as multicore processors scale to 100s of cores and 100+ MB of on-chip cache. Reuse distance (RD) analysis can help architects evaluate multicore memory performance more efficiently. Unfortunately, locality in multicore processors depends on how per-thread memory reference streams interleave. Reliance on memory interleaving makes multicore locality profiles architecture dependent, limiting their ability to analyze different configurations. For loop-based parallel programs, however, threads are typically symmetric and exhibit similar locality characteristics. Such thread symmetry makes multicore RD analysis tractable: locality profiles remain stable with respect to cache capacity scaling, and change systematically with core count and problem size scaling.This project is exploring several research directions related to multicore RD analysis for loop-based parallel programs. First, it is characterizing how Concurrent RD and per-thread RD profiles for symmetric threads vary with processor and problem scaling. Second, it is developing techniques to predict these profile variations. Simple prediction techniques such as reference groups, as well as more sophisticated parametric and non-parametric learning approaches, are being studied. Finally, it is applying the new RD analysis to explore large-scale multicore design spaces, identifying good cache hierarchy organizations. It is also using the RD analyses to improve existing memory performance enhancement techniques such as multithreading and locality optimization.