XPS: FULL: Hardware Software Abstractions: Addressing Specification and Verification Gaps in Accelerator-Oriented Parallelism

考虑到半导体技术缩放的减慢，在可接受的功率约束下维持处理器性能缩放变得越来越具有挑战性。作为回应，微处理器越来越多地使用具有异构并行性和被称为加速器的专用计算单元的复杂架构。 加速器通过避免并行可编程性的开销，以降低的功率/能量提供高计算性能。然而，关键的挑战是，与传统的微处理器CPU不同，加速器没有持久的、可移植的指令集架构（伊萨），而是通过驱动程序或库API进行编程。这增加了将面向加速器的程序移植到具有类似功能但不同实现的其他平台的工作量。增加的工作量对软件成本有严重的影响。此外，事实上，加速器没有正式的，持久的伊萨导致增加的验证复杂性的时候，它已经是在未来的计算平台的设计的限制因素。这项工作的智力价值是，该研究正在开发指令级抽象（ILAs），将伊萨概念扩展到加速器，以解决这些编程和验证挑战。ILA提供了加速器将在每次调用时执行的可见状态更新的正式和高级摘要。 项目？的更广泛的意义和重要性是工作？ILA有两个组成部分：指定状态更新和指定内存一致性模型，即，允许的状态更新相对于其他并行计算元件的顺序。该研究开发了ILA方法，这些方法（i）在加速器之间是统一的，（ii）与可编程处理器的伊萨对称，（iii）在计算（状态变化）和存储器（数据/存储状态更新）抽象之间是统一的。为了显示ILA的价值，研究开发：（一）ILA规范机制的一套丰富的加速器，（二）合成技术和工具，自动生成这些ILA，（三）验证技术和工具，检查这些抽象的实现和（四）进一步的工具，使ILA包括全系统架构仿真。通过这些努力，这项工作解决了加速器为导向的系统的设计和部署的基本软件可移植性和验证的差距。

Given slowdowns in semiconductor technology scaling, it has become increasingly challenging to maintain processor performance scaling at acceptable power constraints. In response, microprocessors increasingly use complex architectures with heterogeneous parallelism and specialized compute units known as accelerators. Accelerators provide high compute performance at reduced power/energy by avoiding the overhead of instruction-programmability. The key challenge, however, is that unlike traditional microprocessor CPUs, accelerators have no durable, portable instruction set architecture (ISA), and instead are programmed via drivers or library APIs. These increase the effort of porting accelerator-oriented programs to other platforms with similar functionality but different implementations. The increased effort has serious consequences for software cost. Furthermore, the fact that accelerators have no formal, durable ISA causes increased verification complexity at a time when it is already the limiting factor in the design of future computing platforms. The intellectual merits of this work are that the research is developing Instruction-Level Abstractions (ILAs) that extend the ISA concept to accelerators in order to address these programming and verification challenges. ILAs offer a formal and high-level summary of the visible state updates that an accelerator will perform on each invocation. The project?s broader significance and importance are the work?s ability to impact industry designs of future accelerator-based computing platforms and thereby help sustain the US computing industry.There are two components to an ILA: specifying the state updates, and specifying the Memory Consistency Model, i.e., the permitted ordering of state updates relative to other parallel compute elements. The research develops ILA methodologies that are (i) uniform across accelerators, (ii) symmetric with the ISA of instruction-programmable processors and (iii) unified across both computation (state change) and memory (data/storage state update) abstractions. To show the value of ILAs, the research develops: (i) ILA specification mechanisms for a rich set of accelerators, (ii) synthesis techniques and tools for generating these ILAs automatically, (iii) verification techniques and tools that check these abstractions against implementations and (iv) further tools enabled by ILAs including full-system architectural simulation. Through these efforts, this work addresses fundamental software portability and verification gaps in the design and deployment of accelerator-oriented systems.