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SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability

SHF: Medium: Collaborative Research: Machine Learning Enabled Network-on-Chip Architectures for Optimized Energy, Performance and Reliability
SHF:中:协作研究:支持机器学习的片上网络架构,可优化能源、性能和可靠性
批准号:
1702496
负责人:
D Brian Ma
金额:
$25.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2017
资助国家:
美国
项目状态:
已结题
起止时间:
2017-06-01 至 2021-05-31

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中文摘要
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英文摘要
Network-on-Chip (NoC) architectures have emerged as the prevailing on-chip communication fabric for multicores and Chip Multiprocessors (CMPs). However, as NoC architectures are scaled, they face serious challenges. A key challenge in addressing optimized NoC architecture design today is the plethora of performance enhancing, energy efficient and fault tolerant techniques available to NoC designers and the large design space that must be navigated to simultaneously reduce power, improve reliability, increase performance and maintain QoS. This research proposes a new cross-layer, cross-cutting methodology spanning circuits, architectures, machine learning algorithms, and applications, aimed at designing energy-efficient, reliable and scalable NoCs. This research will result in (1) novel cross-layer design techniques that take a holistic approach of simultaneously reducing power consumption, while still achieving reliability and performance goals for NoCs, (2) a fundamental understanding of the use of hardware-amenable ML for NoC design optimization, (3) software and hardware techniques for monitoring and collecting critical data and key design parameters during network execution to optimize NoC design, and (4) modeling and simulation tools that will improve the architecture community's design methodologies for evaluating scalable NoCs. The proposed research bridges a very important gap between hardware architects who design power management and fault tolerant techniques at the circuit and architecture level and machine learning scientists who develop predictive and optimization techniques. Due to its cross-cutting nature, the proposed research has the potential to significantly transform the design of next-generation CMPs and System-on-Chips (SoCs) where complex decisions have to be made that affect the power, performance and reliability. The research will also play a major role in education by integrating discovery with teaching and training. The PIs are committed and will continue to expand on outreach activities as part of the proposed project by making the necessary efforts to attract and train minority students in this field.
期刊论文(3)
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会议论文
18.1 A Self-Health-Learning GaN Power Converter Using On-Die Logarithm-Based Analog SGD Supervised Learning and Online T j -Independent Precursor Measurement
18.1 使用基于片内对数的模拟 SGD 监督学习和在线 T j 独立前体测量的自健康学习 GaN 功率转换器
DOI: 10.1109/isscc19947.2020.9062999
发表时间: 2020
期刊: 2020 IEEE International Solid- State Circuits Conference - (ISSCC
影响因子: --
作者: [Huang, Yuanqing, Chen, Yingping, Ma, D. Brian]
通讯作者: Ma, D. Brian
EMI-Regulated GaN-Based Switching Power Converter With Markov Continuous Random Spread-Spectrum Modulation and One-Cycle on-Time Rebalancing
具有马尔可夫连续随机扩频调制和单周期准时再平衡功能的 EMI 调节 GaN 开关电源转换器
DOI: 10.1109/jssc.2019.2931439
发表时间: 2019
期刊: IEEE Journal of Solid-State Circuits
影响因子: 5.4
作者: [Chen, Yingping, Ma, D. Brian]
通讯作者: Ma, D. Brian
DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning
DozzNoC:利用机器学习通过低延迟稳压器减少 NoC 中的静态和动态能量
DOI: 10.1109/ipdps47924.2020.00011
发表时间: 2020
期刊: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS
影响因子: --
作者: [Clark, Mark, Chen, Yingping, Karanth, Avinash, Ma, Brian, Louri, Ahmed]
通讯作者: Louri, Ahmed
Collaborative Research: Heterogeneous Integration of Patterned 3-D Nanotube Supercapacitators on CMOS
  • 批准号:
    1110408
  • 项目类别:
    Standard Grant
  • 资助金额:
    $14.65万
  • 财政年份:
    2010
  • 负责人:
    D Brian Ma
  • 依托单位:
Collaborative Research: Heterogeneous Integration of Patterned 3-D Nanotube Supercapacitators on CMOS
  • 批准号:
    0925678
  • 项目类别:
    Standard Grant
  • 资助金额:
    $16.74万
  • 财政年份:
    2009
  • 负责人:
    D Brian Ma
  • 依托单位:
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