Pattern Adaptable Antenna Arrays for Networks on Chips in Massively Multicore Systems

该项目的目标是通过创造专门的片上天线来推动科学计算，这些天线可以放置在高性能计算机中，以便在处理器芯片之间无需使用电线进行高速数据传输。这将取代硬连线互连，并将允许轻松和无缝地重新路由信号，以提高系统吞吐量和可靠性。这可能会对涉及海量数据处理的大规模科学计算和应用程序产生重大影响。天线模块模仿了“片上无线基站”的概念，因为天线在计算机内部发送信号，以实现更快、更高效的处理输出。该项目将首次展示一种小型、紧凑和可重新配置的天线模块，该模块将被设计为高频，以便将它们放置在计算机中。选择特定的频率是为了使天线不会辐射到计算机本身之外。研究方法包括通过仿真来设计天线，通过在环境中演示和测试天线来验证天线是否达到了预期的目标。这项研究的影响是提高解决新兴科学应用中日益苛刻的计算问题的能力。这项技术可能会打破计算中观察到的性能障碍，并创建新的计算体系结构。该项目将把研究与教育结合起来，并为高年级本科生和研究生提供融合计算、互联、高频模拟和测量领域的学习机会。高中生和大学新生将能够在一个新的新生课程模块中探索技术，该模块将向大学生介绍电气工程方面的不同机会。亚利桑那大学电气和计算机工程科学硕士在线课程的信号完整性课程将加强研究生课程的提供。这个项目将创建和演示首批芯片兼容的天线阵列之一，允许实时方向图适配用于大规模多核计算。天线将设计在一个单独的天线模块上，该模块包括一个方向图可重新配置的天线，以允许在水平方向上重新定向天线方向(芯片到芯片)。该阵列将实现至少八个独特的波束位置，以允许与邻近核心进行通信。该天线模块有几个新颖的组件：它很薄(1-2毫米)，包括一个3D(多层)堆叠波束形成器，并且可以使用倒装芯片(焊球凸起)连接到收发器。在系统层面，该项目将展示一种新颖的系统设计，使用可重新配置的无线链路来简化I/O(输入/输出)架构，并通过可重新配置的数据路径绕过断开的链路来提高系统可靠性。该项目包括开发考虑天线和传播特性的准确链路模型。这将使用物理天线的细节(例如它们在操作环境中的方向图特征)提供准确的网络规划，并使计算机网络拓扑能够最优化。原型天线将被制造和测量，使用60 GHz收发信机评估板的演示测试台将验证链路模型。

The goal of this project is to advance scientific computing by creating specialized on-chip antennas that can be placed inside high performance computers to allow high-speed data transfers between processor chips without using wires. This will replace hardwired interconnections and will allow rerouting of signals easily and seamlessly to improve system throughput and reliability. This may have significant impact on large-scale scientific computing and applications involving huge amounts of data processing. The antenna modules mimic "wireless-base-station-on-chip" concept since the antennas route signals inside the computer to achieve much faster and more efficient processing output. The project will demonstrate for the very first time a small compact and reconfigurable antenna module to be designed at high frequencies so they can be placed in computers. The specific frequency is chosen so that the antennas do not radiate beyond the computer itself. The research methods include designing the antenna by using simulations, and by demonstrating and testing antennas in the environment to verify that the desired goals are met. The impact of this research is to improve the capability of solving increasingly demanding computing problems in emerging scientific applications. This technology can potentially break performance barriers observed in computing and create new computing architectures. The project will integrate research with education, and provide learning opportunities merging the areas of computing, interconnects, high frequency simulations, and measurements to senior-level undergraduate students and graduate students. High school students and college freshmen will be able to explore technologies in a new freshman course module that introduces university students to different opportunities in electrical engineering. Graduate student course offerings will be enhanced with a signal integrity course for the online Masters of Science in Electrical and Computer Engineering program at the University of Arizona. Hands-on and engagement activities will be offered to train and prepare students for their future career in industry or academia.This project will create and demonstrate one of the first chip-compatible antenna arrays that allow real-time pattern adaptation for use in massively multicore computing. The antennas will be designed on a separate antenna module that includes a pattern-reconfigurable antenna to allow for redirection of the antenna patterns in the horizontal direction (chip to chip). The array will achieve at least eight unique beam positions to allow communication to neighboring cores. The antenna module has several novel components: it is thin (1-2 mm), includes a 3D (multilayer) stacked beamformer, and can be connected to a transceiver using flip-chip (solder ball bump) attachment technologies. On system level, the project will demonstrate a novel system design using reconfigurable wireless links to simplify the I/O (Input/Output) architecture and improve system reliability with reconfigurable data paths that work around broken links. The project includes developing accurate link models that takes into account antenna and propagation characteristics. This will provide for accurate network planning using details of the physical antennas such as their pattern characteristics in the operating environment, and enable optimization of the computer network topology. Prototype antennas will be fabricated and measured, and demonstration test beds using 60 GHz transceiver evaluation boards will validate the link models.