SBIR Phase I: High Fidelity EUV PhotoMasks

小型企业创新研究(SBIR)第一阶段项目的更广泛影响/商业潜力是通过制造7纳米及更小规模的集成电路来推动下一代先进的计算能力和性能，集成电路是电子系统的基本单元。今天？S的每个中央处理器(CPU)都包含7.2Bn芯片，每年生产超过1.2千万亿个芯片，以满足计算需求。下一代技术预计将通过传统计算和潜在的神经形态范式实现人工智能和机器学习，使自动驾驶汽车和智能建筑等变革性应用成为现实。随着摩尔？S定律继续引领技术进步的步伐，芯片制造商将在未来三代技术中部署新的极紫外(EUV)光刻工具，使用13.5纳米的光将集成电路或芯片架构图案化为硅片。芯片制造商努力在2019年实现EUV技术的就绪。随着人口增长超过70亿，全球对下一代电子产品的需求永远在增长。然而，全球电子供应不断面临着降低成本和提供超越摩尔？S定律的技术的挑战。拟议的项目解决了与光刻工具及其组件的7纳米节点大批量制造相关的挑战。例如，EUV光掩模是一种商品化程度很高的部件，它将集成电路设计图案化并复制到硅片中。目前的EUV光掩模的制造成品率不是很理想，只有60%左右，并且在其结构制造过程中会出现缺陷。在操作使用期间，光掩模受到EUV等离子体光源产生的碎片的损害，这些碎片植入掩模并不可避免地在晶片中复制，破坏集成芯片图案。在大批量生产中，这些问题表现在晶片成品率、掩模的可重用性，并推动了对高成本实时检测和计量的需求。提出了一种新的EUV光掩模，该掩模具有更强的抗缺陷能力、更高的制造成品率、更高的操作中掩模的可重用性和更长的使用寿命。该项目的目标是评估EUV掩模设计的新集成架构，开发更高成品率的制造工艺，并表征EUV性能。更坚固的光掩模减少了现场测量和检查所需的资本支出，并最终降低了下一代电子产品的成本。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to drive the next generation of advanced computing power and performance, by manufacturing integrated circuits, the fundamental units of electronic systems, at length scales of 7 nm and smaller. Today?s central processing units (CPUs) each contain 7.2 Bn chips and over 1.2 sextillion chips are manufactured per year to meet computing demands. Next generation technology is expected to enable artificial intelligence and machine learning through both conventional computing and potentially neuromorphic paradigms, bringing to reality transformative applications such as self-driving cars and smart buildings. As Moore?s law continues to set the pace of technological advancement, chipmakers will deploy new EUV (Extreme Ultraviolet) lithography tools, using light of 13.5 nm to pattern integrated circuits or chip architecture into silicon wafers, for the next three generations of technology. Chipmakers strive to bring about the readiness of EUV technology in 2019. The global demand for next generation electronics is forever increasing as the population grows above 7 Bn. However, the global supply of electronics constantly faces challenges to reduce costs and deliver technology beyond Moore?s Law.The proposed project addresses the challenges related to high volume manufacturing at the 7 nm node for lithography tools and its components. For example, an EUV photomask, a high commodity component, patterns and replicates integrated circuit design into silicon wafers. Current EUV photomasks have a sub-optimal manufacturing yield of ~60% and suffer from defectivity which arises during fabrication of its architecture. During operational use the photomask sustains damage from the debris generated by the EUV plasma light source that implants in the mask and inevitably replicates in the wafer, destroying the integrated chip pattern. In high volume manufacturing, these issues manifest in the wafer yield, the reusability of a mask, and drive the need for high cost real-time inspection and metrology. A new EUV photomask which promises greater robustness to defects, a higher manufacturing yield, more reusability of masks in operations and a longer lifetime is presented. The goals of the project are to evaluate new integrated architecture for the EUV mask design, develop a higher yield fabrication process and characterize the EUV performance. More robust photomasks reduce the capital outlay required for in-situ metrology and inspection and ultimately bring down the cost of next generation electronics.