SHF:Medium:Collaborative Research: Decentralized On-Chip Infrastructure for Robustness and Portability in Heterogeneous Multicores

当新的硬件选择出现在现代计算机系统中时，必须重写或零售软件代码才能在新系统上工作。其结果是，应用程序代码库不能从一代无缝移植到另一代。更糟糕的是，即使在给定的系统上，它们通常也不能完全或灵活地适应执行过程中的动态变化。这项工作将缓解异类平台的复杂性、可移植性和健壮性挑战，同时还将继续获得高性能。利用研究团队在开源软件发布和课程开发方面的经验，该项目将分发在这些研究项目中开发的工具，并通过现有的关于异类体系结构的设计和编程的课程教授这些新工具。解决该项目的研究挑战需要从以处理器为中心的观点转向旨在管理通信问题的更广泛的视角。研究小组将引入“硬件垫片”的概念，可用于一系列用途，如充当预取器、在不同通信协议之间转换或协助设计者指定的属性的动态验证。该项目将自动化静态或动态垫片的设计和合成，以验证设计者为其提供一套排序规范的任意异类多核的内存一致性。拟议的研究活动将展示性能、功能健壮性和代码可移植性方面的收益，因为应用程序是在所使用的处理器和专用硬件加速器的数量和类型方面存在显著差异的系统上编译和执行的。该奖项反映了NSF的法定使命，并已通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

When new hardware options emerge in modern computer systems, software code must be rewritten or retailored to work on the new systems. The result is that application code-bases do not seamlessly port from one generation to another. Even worse, they often cannot fully or nimbly adjust to dynamic variations during execution even on a given system. This work will mitigate the complexity, portability, and robustness challenges of heterogeneous platforms, while also continuing to garner high performance. Leveraging the research team's experience in open-source software release and curriculum development, this project will distribute the tools developed in these research thrusts as well as teach these new tools via an existing course on design and programming of heterogeneous architectures.Addressing the research challenges of this project requires moving away from a processor-centric viewpoint, and towards a broader perspective aimed at managing communication issues. The research team will introduce the concept of "hardware shims" that can be employed for a range of uses such as acting as prefetchers, translating between different communication protocols, or assisting with dynamic verification of properties specified by the designer. The project will automate the design and synthesis of static or dynamic shims that can verify the memory consistency of an arbitrary heterogeneous multicore for which the designer provides a set of ordering specifications. The proposed research activities will demonstrate gains in performance, functional robustness, and code portability as the application is compiled and executed on systems that differ significantly in terms of the number and type of processors and specialized hardware accelerators that they use.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.