SBIR Phase II: In-Memory Artificial Neural Network

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力是由一种新型的数据处理架构提供的，该架构利用高并行内存计算来实现某些重复性和数据密集型功能。传统的计算机架构通过中央处理器（CPU）收集所有数据。多个CPU内核和非常高的时钟频率用于解决对数据处理能力的需求不断增加的问题。然而，存储器和CPU核心之间的数据传输能力已经成为产生“存储器瓶颈”的限制因素。这种限制是最明显的，在最近和快速发展的人工智能应用程序，部署所谓的神经形态计算技术，这反过来又需要一个非常高的并行计算和内存带宽的比例需求。该项目在内存本身内执行关键的重复操作，利用内存架构的固有并行性，从而避免了大量的数据传输。内存瓶颈的消除为高复杂性神经形态计算应用提供了一条前进的道路，例如用于自动驾驶汽车的自主导航。减少对数据传输和CPU的需求也大大降低了功耗，使各种各样的移动的人工智能application.The拟议的项目调查的系统级集成的挑战，以内存为中心的神经形态计算的方法，并旨在展示一个无缝集成与现有的软件平台，目前使用传统的神经形态计算处理器。新的硬件平台必须与现有软件兼容，以降低市场准入门槛。该第二阶段项目还开发了实际的半导体产品，该产品已在第一阶段作为可行性演示器进行了研究。第二阶段产品基于非易失性高密度存储器架构，因此预计将在功耗和每秒操作数方面提供全部功能。一旦硬件在项目的后半部分可用，这些关键参数将根据当前最先进的技术进行彻底的表征和基准测试。一个预测将概述未来的扩展潜力，使用超高密度的易失性和非易失性存储器面向高复杂性的神经形态计算超出了目前可能使用现有的approaches.This奖项反映了NSF的法定使命，并已被认为是值得的支持，通过评估使用基金会的智力价值和更广泛的影响审查标准。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is provided by a novel data processing architecture, utilizing high-parallel in-memory computing for certain recurring and data intensive functions. Traditional computer architecture funnels all data through the central processing unit (CPU). Multiple CPU cores and very high clock frequencies are used to address the issue of ever increasing demands on data processing capability. However, the transportation capacity of data between memory and CPU cores has become a limiting factor creating a 'memory bottleneck'. This limitation is most noticeable in the recent and rapid development of artificial intelligence applications which deploy so called neuromorphic computing techniques, which in turn require a very high parallelism in computation and proportional demands on memory bandwidth. This project performs key repetitive operations within the memory itself, leveraging the inherent parallelism of the memory architecture, thereby avoiding a large percentage of the data transport otherwise required. The resulting elimination of the memory bottleneck provides a path forward for high complexity neuromorphic computing applications such as autonomous navigation used for self-driving cars. Reduced demands on data transport and CPU also significantly reduce power consumption, enabling a wide variety of mobile artificial intelligence applications.The proposed project investigates the system level integration challenges of a memory-centric neuromorphic computing approach, and aims to demonstrate a seamless integration with existing software platforms currently using traditional neuromorphic computing processors. It is important for a novel hardware platform to be compatible with existing software in order to lower barriers to market entry. This Phase II project also develops the actual semiconductor product which has been investigated in Phase I as a feasibility demonstrator. The Phase II product is based on a non-volatile high density memory architecture, and as such is expected to provide the full capability in terms of both power and operations per second. Once the hardware is available in the second half of the project, these key parameters will be thoroughly characterized and benchmarked against the current state of the art technology. A projection will be made outlining the future scaling potential using ultra high density volatile and non-volatile memory geared towards high complexity neuromorphic computing beyond what is currently possible using existing approaches.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.