FET: Small: Design Optimization of Silicon Photonic Integrated Circuits under Fabrication Process Variations

硅光子学技术使得利用亚微米硅光子器件实现完全集成的光子电路成为可能。因此，可以开发出小型和移动的光子电路，其可以针对不同的应用执行各种光学功能，但是具有低得多的成本和能耗。然而，有一个基本问题限制了硅光子集成电路的出现：这些电路中的底层硅光子器件对制造工艺的变化非常敏感。事实上，硅光子器件的临界尺寸的纳米级变化大大降低了所得电路的性能，甚至导致电路故障。不幸的是，迄今为止，无法有效地表征和补偿制造工艺变化限制了能够提供硅光子学的真正潜力的具有成本效益的硅光子集成电路的发展。为了解决这个问题，该项目涉及研究实现节能和复杂的硅光子集成电路，用于不同的现实世界的应用，即使在存在变化困扰的组件的情况下也能完全发挥作用。此外，该项目还将为行业参与者和不同层次的学生创造培训机会，以解决现实世界的问题，同时强调将代表性不足的群体纳入其中，从而改善教育基础设施，培养高技能的从业人员。1）硅光子学中的系统和随机过程变化的综合模型，同时结合不确定性的概率和非概率性质; 2）在设计时间期间在制造工艺变化下优化硅光子子电路和电路的框架;以及3）在运行时间期间有效地补偿制造工艺变化的影响的节能电路级解决方案。为了表征不同的变化，将设计新颖的硅光子测试结构和分析算法来模拟不同的制造工艺变化来源及其影响。将开发高效和紧凑的随机分析模型，以广泛探索和优化变化下的硅光子子电路和电路性能。对于设计时优化，硅光子集成电路设计问题将被建模为形式优化问题，以实现在制造工艺变化下的节能和鲁棒电路。通过开发基于自适应光子信号多路复用的运行时自校正机制、鲁棒的信号路由和竞争管理方案以及动态适应变化下的不精确电路行为，将进一步提高制造工艺变化下的性能。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Silicon photonics technology has made it possible to realize fully integrated photonic circuits with sub-micron silicon photonic devices. As a result, small and mobile photonic circuits can be developed that can perform a variety of optical functions for different applications, but with much lower cost and energy consumption. However, there is a fundamental issue that has limited the emergence of silicon photonic integrated circuits: the underlying silicon photonic devices in these circuits are extremely sensitive to fabrication-process variations. Indeed, nanometer-scale variations in the critical dimensions of silicon photonic devices considerably degrade the performance of the resulting circuits and even cause circuit failures. Unfortunately, the inability to efficiently characterize and compensate for fabrication-process variations have so far limited the development of cost-effective silicon photonic integrated circuits capable of delivering the true potential of silicon photonics. To combat this, the project involves research to realize energy-efficient and complex silicon photonic integrated circuits for different real-world applications that will be fully functional even in the presence of variation-plagued components. In addition, this project will create training opportunities for industrial participants and students at different levels to work on real-world problems while emphasizing the inclusion of underrepresented groups, thereby improving the education infrastructure and training highly skilled practitioners.The project contributions will involve developing: 1) comprehensive models of systematic and stochastic process variations in silicon photonics while incorporating both the probabilistic and non-probabilistic nature of uncertainties; 2) a framework to optimize silicon photonic sub-circuits and circuits under fabrication-process variations during design-time; and, and 3) energy-efficient circuit-level solutions to efficiently compensate for the impact of fabrication-process variations during run-time. For characterizing different variations, novel silicon photonic test structures and analytical algorithms will be designed to model different sources of fabrication-process variations and their impact. Efficient and compact stochastic analytical models will be developed to extensively explore and optimize silicon photonic sub-circuit and circuit performance under variations. For design-time optimization, the silicon-photonic integrated-circuit design problem will be modeled as a formal optimization problem to realize energy-efficient and robust circuits under fabrication-process variations. The performance under fabrication-process variations will be further improved by developing run-time self-correction mechanisms based on adaptive photonic signal multiplexing, robust signal routing and contention-management schemes, and dynamic adaptations for inexact circuit behavior under variations.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.