Collaborative Research: SHF: Small: Optimization of Memory Architectures: A Foundation Approach

该项目提出了一种模型驱动的现代计算机体系结构的内存系统性能优化的基本方法，开发了一套内存体系结构优化方法和工具，这些方法和工具在理论上得到了验证，并在经验上适用于现代内存体系结构设计。该项目的成果将显着提高性能建模和优化技术，用于设计和评估现代计算机系统中的内存架构，具有深度和多样化的内存系统层次结构，异构内存设备和复杂的数据密集型应用程序，包括大数据，云和数据中心以及高性能计算应用程序。该项目的研究结果将改进方案研究员教授的各种课程的内容。该项目计划利用印度理工学院，特别是为少数民族服务的金融情报机构的机构努力，积极招收少数民族学生。该项目将使教育和推广活动与现有的研究和教育中心保持一致。CPU和内存速度之间日益增长的差距导致内存访问成为现代计算机体系结构中严重的性能瓶颈。 在过去的25年里，解决这个“内存墙”问题的尝试支撑了计算机体系结构设计的技术创新。该研究的目的是显着扩展以前的内存模型，并创建一个实用的内存架构性能建模和优化框架，可以捕获的数据局部性，数据并发性，访问延迟和多层内存架构的综合影响，为真实的应用程序和真实的系统。一个模拟驱动的方法将开发详细的真实系统的测量和性能分析，以检查潜在的好处，并确定各种内存架构设计的性能问题。更具体地说，本项目将沿着沿着三个研究方向发展：（1）发展理论和架构基础，以解决与分层异构存储器架构相关的基本问题，并研究将建模和优化框架应用于各种存储器架构的实际方面;（2）针对特定存储器架构执行模型驱动的存储器架构设计和优化，包括分解存储器系统GPU，以及具有包括非易失性存储器的混合存储器设备的深存储器层次结构;以及（3）开发嵌入有性能建模和优化框架的存储器体系结构模拟器，并进行模拟研究和真实的系统测量以评估存储器性能，该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

This project proposes a foundational approach to model-driven performance optimization of memory systems for modern computer architectures, with the development of a set of memory-architecture optimization methods and tools that are theoretically proven and empirically feasible for modern memory architecture design. The outcome of this project will significantly improve the performance modeling and optimization techniques for designing and evaluating memory architectures in modern computer systems, featuring deep and diverse memory-system hierarchies, heterogeneous memory devices, and complex data-intensive applications, including big-data, cloud and data centers and high-performance computing applications. The findings of this project will improve the content of various courses that the PIs teach. This project plans to proactively recruit minority students by taking advantage of the institutional efforts at IIT and especially at FIU, which is a minority-serving institution. This project will align education and outreach activities with an existing research and education center.The growing disparity between CPU and memory speed causes memory accesses to become a severe performance bottleneck in modern computer architectures. Attempts to solving this “memory wall” problem underpin technological innovations in computer-architecture design over the last two and half decades. The objective of the research is to significantly extend prior memory models and create a practical memory-architecture performance-modeling and optimization framework that can capture the combined effects of data locality, data concurrency, access latency, and multi-tier memory architecture for real applications and on real systems. A simulation-driven approach will be developed with elaborate real-system measurements and performance analyses to examine the potential benefits and identify the performance issues of various memory-architecture designs. More specifically, this project will develop along three research directions: (1) developing theoretical and architectural foundations to address both fundamental questions related to the tiered heterogeneous memory architectures and investigate practical aspects of applying the modeling and optimization framework for various memory architectures; (2) performing model-driven memory-architecture design and optimization for specific memory architectures, including disaggregated memory system, GPU, and deep-memory hierarchy with hybrid memory devices including non-volatile memory; and (3) developing the memory architecture simulator embedded with the performance modeling and optimization framework, and conducting simulation studies and real system measurements to evaluate memory performance, and compare design alternatives and trade-offs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.