Nyquist-Rate AD-Converters with Signal Dependent Sampling Rate

目的是开发奈奎斯特ADC中动态采样率的方法。目标是不增加额外的模拟电路，如额外的窗口比较器的努力和功率的方法。本文的第一个目标是分析带反馈DAC的ADC中量化器的输出信号特性，第二个目标是对反馈环路和异步ADC的处理过程进行数学描述和建模。在此过程中，功能块被合并，并推导出异步ADC规则和标准的稳定性标准。第三步，在演示器（测试芯片）上验证理论工作。我们的主要目标不仅仅是推动FOM，而是获得异步ADC的模型套件。测试芯片的模块化概念，具有各种评估选项，以及在65 nm设计和ADC设计方面的经验，可显著降低流片风险。评估的一个关键方面是理想特性和测量特性的匹配。应在原始模型中实现由于寄生效应而导致的与正常条件的偏差，以实现对系统的充分理解。

The objective is to develop methods for dynamic sampling rates in Nyquist ADCs. The ambition are methods that do not increase the effort an power due to additional analog circuitry, like additional window comparators. Starting point is the characteristics of the output signal of the quantiser in ADCs with feedback DAC.The second objective is a mathematical description and model of the feedback loop and the processing of the asynchronous ADC. In doing so the functional blocks are combined and stability criteria are derived for rules and standards for asynchronous ADCs.In a third step the theoretical work is verified on a demonstrator (test chip). It is not the primary goal just to push the FOM, but to get a model kit for asynchronous ADCs. A modular concept of the test chip with various options for evaluation and the experience in 65nm-designs and ADC-designs significantly reduces the risk of the tape out.A key aspect of the evaluation is the matching of ideal and measured characteristics. Deviations from normal conditions due to parasitic effects should be implemented in the original model to achieve full understanding of the system.