IRES Track 1: Impact of Emerging Information Processing Technologies on Architectures and Applications – a U.S.—French Partnership

30多年来，MOS场效应管(MOSFET)一直是现在每年价值4000亿美元的半导体行业的中流砥柱，用于在芯片上处理和存储信息。不断缩小晶体管的能力(也就是摩尔定律)推动了计算机处理器大小和性能的指数级改进。不幸的是，晶体管的规模已经受到物理、成本和制造相关问题的限制。此外，数据中心功率预算、空气冷却的实际限制以及物联网(IoT)中移动和边缘连接设备的兴起等限制，都使能效成为同样重要的设计驱动因素。IRES项目的动机是(I)半导体行业寻找器件/技术以继续历史上与摩尔定律相关的性能扩展趋势，以及(Ii)需要新技术和计算机架构来满足边缘新兴应用空间的计算需求。来自圣母大学(ND)的研究人员和法国里昂中央学院的导师将与ND的计算机科学与工程(CSE)学生以及与ND领导的研究中心有关联的其他机构的学生合作，研究由新兴技术支持的新计算机体系结构最终将如何影响应用级驱动程序。通过与AnBryce学者倡议、QuestBridge学者、STEM学者和POSSE计划的领导人合作，将招募一支强大的、多样化的IRES研究人员队伍。一个首要目标是从大学各系的少数族裔、低收入和第一代学生群体(及其组合)中寻找优秀的IRES候选人，他们的学术重点将与本提案的学术重点保持一致。还将咨询负责学生发展的助理院长(负责管理工程学和一年级工程学的妇女)，以确定有前途的女学生，以及来自低收入/第一代/其他少数群体的学生。在更多的技术细节中，技术、体系结构和应用的耦合是必不可少的，因为新设备的独特特征将导致从根本上不同于现有最先进技术的电路和体系结构，并可能导致用于解决给定问题的新计算模型。应用级分析是判断一款新设备最终效用的最佳方式，通常也是唯一的方式。特别强调了新技术和模型在应用于机器学习时的影响(通过硬件支持可以用有限数量的训练数据学习的算法，以及支持边缘有效训练/推理的模拟硬件)。还考虑了合并逻辑和存储器以支持安全处理(例如，AES和同态加密)的硬件体系结构。还将对建议的硬件解决方案与最先进的硬件解决方案进行系统基准比较。鉴于美国对技术驱动的硬件架构的重视，以及欧洲对物联网硬件解决方案的关注，这种关注非常适合IRES团队。该项目由国际科学与工程办公室(OISE)资助。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

For over 30 years, MOS field effect transistors (MOSFETs) have been the mainstay of the now $400B/year semiconductor industry and are used to both process and store information “on chip.” The ability to continuously make transistors smaller (aka Moore's Law scaling) has fueled exponential improvements in computer processor size and performance. Unfortunately, transistor scaling has become limited by physics, cost, and manufacturing-related issues. Furthermore, constraints such as data center power budgets, the practical limits of air cooling, and the rise of mobile and edge connected devices in the internet of things (IoT) have all made energy efficiency an equally important design driver. IRES projects are motivated by (i) the semiconductor industry's search for devices/technologies to continue performance scaling trends historically associated with Moore's Law, and (ii) the need for new technologies and computer architectures to meet the computational needs of emerging application spaces at the edge. Researchers from the University of Notre Dame (ND) and mentors from Ecole Centrale de Lyon in France will work with Computer Science and Engineering (CSE) students from ND, as well as students from other institutions that are affiliated with ND led research centers, to study how new computer architectures that are enabled by emerging technologies will ultimately impact application-level drivers. A strong, diverse cohort of IRES researchers will be recruited via collaborations with leaders from the AnBryce Scholars Initiative, QuestBridge Scholars, STEM Scholars, and Posse programs. An overarching goal is to identify outstanding IRES candidates from minority, low-income, and first-generation student groups (as well as combinations thereof) from university departments whose academic focus would be in-line with that of this proposal. The Assistant Dean of Student Development (who oversees women in engineering and first-year engineering) will also be consulted to identify promising female students, as well as students from low income/first generation/other minority groups. In more technical detail, the coupling of technology, architecture, and applications is essential as the unique characteristics of new devices will lead to circuits and architectures that are fundamentally different from the existing state-of-the-art and may lead to new computational models for solving a given problem. Application-level analysis is the best – and frequently the only – way to judge the ultimate utility of a new device. A particular emphasis is placed on the impact of new technologies and models when applied to machine learning (via hardware support for algorithms that can learn with limited amounts of training data, as well as analog hardware to support efficient training/inference at the edge. Hardware architectures that merge logic and memory to support secure processing (e.g., AES and homomorphic encryption) are also considered. Systematic benchmarking of proposed hardware solutions against the state-of-the-art will also be done. This focus is well-suited for this IRES team given a US emphasis on technology driven hardware architectures, and a European focus on hardware solutions for the IoT. This project is funded by the Office of International Science and Engineering (OISE).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.