Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications

该项目将开发一个框架，用于快速和准确地探索应用级工作负荷的设计空间，假设采用技术使能的内存计算(IMC)，目前正在为一系列应用空间(人工智能/机器学习、生物信息学、图形处理等)进行研究。随着越来越多的计算工作负载必须处理不断增长的数据量，IMC引起了人们的极大兴趣。通常，与数据从计算机内存传输到处理器相关的能量和延迟可能会超过处理本身的成本。因此，将处理和内存放在一起是非常可取的。该项目的工作将产生一个公开可用的、经过管理的框架，该框架利用现有的设备模型和设计工具，并结合新的设备模型和设计工具，以适当评估具有大规模应用程序级工作负载的IMC设计空间。将开发一个建模和评价基础设施，以应对上述设计/评价挑战，因为显然需要探索广阔的设计空间。该项目的研究人员还将与K-8教师合作，用让学生接触计算机科学基本概念和技能的材料来补充现有的STEM课程。这一点尤其相关，因为计算机科学概念现在是在全州范围的标准化考试中进行评估的。要探索IMC设计空间，必须学习设备级建模、电路/架构级建模、设备非理想性(例如，变化)分析，以及如何集成针对特定应用级工作负载的不同架构解决方案。在IMC领域中，(I)候选技术的数量很大且不断变化，(Ii)存在多个候选IMC电路和架构--例如，在阵列外围(CAP)、内容可寻址存储器(CAM)和交叉开关的计算，(Iii)IMC解决方案可能更容易受到设备变化/非理想性的影响，并且这种影响必须在应用层捕捉，(Iv)新兴技术使能的IMC解决方案可以与现有架构解决方案和/或各种异质设计一起使用，以及(V)实际上可以考虑无限数量的应用程序级映射/潜在的算法改变。对于器件模型，由于对该技术的不断增长的兴趣以及考虑单片3D处理/存储系统的需要，故意将重点放在铁电器件上，即，线的前端的硅铁电场效应晶体管、线的后端的金属氧化物铁电场效应晶体管和多栅极的铁电场效应晶体管。对于IMC电路/体系结构，该项目将扩展和开发两种不同类型的内存计算的建模/评估工具--(I)CAMS(可以报告与给定查询最匹配的内存条目)和(Ii)CAP。对于CAM，有代表性的工作包括预测二进制、三值、多电平和模拟CAM阵列的品质因数(读/写能量和延迟等)。使用不同的非易失性存储器实现的设计，用于不同的匹配功能。还将考虑确定最佳的CAM阵列大小和其他设计参数。还将对不同NVM的CAP设计进行评估。对于应用程序，将评估针对MLPerf应用程序子集的基于IMC结构的解决方案。MLPerf代表一个由人工智能领导者组成的联盟，他们为愿景、语言等派生了相关的工作量。该奖项反映了NSF的法定使命，并通过使用基金会的智力优点和更广泛的影响审查标准进行评估，被认为值得支持。

This project will develop a framework for rapid and accurate design-space explorations of application-level workloads assuming technology-enabled in-memory computing (IMC), which is at present being investigated for a range of application spaces (AI/machine learning, bioinformatics, graph processing, etc.). IMC is of great interest as more and more compute workloads must process ever growing amounts of data. Frequently, the energy and latency associated with data transfer from a computer’s memory to a processor can overwhelm the cost of the processing itself. As such, it is highly desirable to co-locate processing and memory. Work in the project will result a publicly available, curated framework that leverages both existing device models and design tools, and that incorporates new device models and design tools to properly evaluate the IMC design space with at-scale, application-level workloads. A modeling and evaluation infrastructure will be developed to address the above design/evaluation challenges as there is an obvious need to explore a vast design space. Investigators in this project will also work with K-8 teachers to augment existing STEM curricula with material that exposes students to fundamental concepts and skills in computer science. This is especially relevant as computer science concepts are now assessed on state-wide standardized tests. Students from under-represented groups will be recruited and mentored via REU experiences.To explore the IMC design space, device-level modeling, circuit/architectural-level modeling, device non-ideality (e.g., variation) analysis, and ways to integrate heterogeneous architectural solutions that target specific application-level workloads must all be studied. In the IMC space, (i) the number of candidate technologies is large and ever-changing, (ii) multiple candidate IMC circuits and architectures – e.g., computing at the array periphery (CAP), content addressable memories (CAMs) and crossbars – exist, (iii) IMC solutions may be more susceptible to device variations/non-idealities, and this impact must be captured at the application level, (iv) emerging technology-enabled IMC solutions may be used with existing architectural solutions and/or in a variety of heterogenous designs, and (v) there are effectively an infinite number of application-level mappings/potential algorithmic changes that one might consider. With respect to device models, there is a deliberate focus on ferroelectric devices – i.e., front-end-of-line silicon ferroelectric field effect transistors, back-end-of-line metal-oxide ferroelectric field effect transistors, and multi-gate ferroelectric field effect transistors – owing to ever-growing interest in this technology as well as the need to consider monolithic 3D processing/memory systems. For IMC circuits/architectures, this project will expand and develop modeling/evaluation tools for two different “flavors” of computing in memory – (i) CAMs (that can report memory entries that best match a given query) and (ii) CAP. For CAMs, representative efforts include projecting figures of merit for binary, ternary, multi-level, and analog CAM arrays (read/write energy and latency, etc.) designs implemented with different non-volatile memories, for different matching functions. Determining optimal CAM array sizes and other design parameters will also be considered. Evaluation of CAP designs for different NVMs will also be developed. For applications, solutions based on IMC fabrics for a subset of applications from MLPerf will be evaluated. MLPerf represents a consortium of AI leaders who have derived relevant workloads for vision, language, etc.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.