III-V semiconductor nanowires: correlation of local electronic structure, conductivity, and carrier lifetime

半导体纳米线(NW)是一种很有前途的新型电子器件和光电子器件的构建块，具有非常广泛的范围，可以根据尺寸、几何形状和不同的晶体结构来调整电子性质。即使没有晶体结构作为大块材料也可以生产。因此，纳米粒子被认为具有从太阳能电池到纳米电子学的许多潜在应用。然而，许多基本方面仍有待阐明。其中有两点特别相关：首先，西北向几何结构导致了非常高的表面积与体积比。因此，表面诱导效应，如费米能级钉扎，对纳米粒子的性质和基于它们的器件的功能起着很大的作用。其次，除了故意插入的异质界面外，NW可能还经常包含多型插入、孪生边界和堆叠断层。它们影响电子性质，引入能带偏移，从而影响导电性和载流子寿命。因此，这个项目的总体目标是用原子分辨率研究侧壁表面、缺陷和界面的电子性质，并将它们与III-V半导体纳米管的导电性和载流子寿命相关联。特别是，我们计划在第一步中研究(I)不同III-V材料成分和不同类型的侧壁表面可能的费米能级钉扎、能量位置及其物理来源，(Ii)界面态、能带排列和偏移量以及异质界面附近的带隙，(Iii)平面缺陷和多型插入的电子性质，以及(Iv)表面费米能级钉扎与内部结、界面和缺陷的相互作用。在第二步中，这些性质将与NW的导电性和载流子寿命相关联。主要目的是阐明非本征表面钉扎、界面缺陷和平面缺陷以及有意结合的点缺陷如何影响NW的导电性和载流子寿命。

Semiconductor nanowires (NW) are promising building blocks of novel electronic and optoelectronic devices, with an exceptional wide range for tailoring electronic properties by size, geometry, and different crystallographic structures. Even crystallographic structures being not available as bulk materials can be produced. Hence, NWs are considered for many potential applications ranging from solar cells to nanoelectronics. However, many fundamental aspects remain to be elucidated. Two of them are particularly relevant: First, the NW geometry leads to a very high surface-to-volume ratio. Consequently, surface-induced effects, such as Fermi level pinning, play a large role for the properties of NWs and the functionality of devices based on them. Second, NWs may contain frequently polytype insertions, twin boundaries, and stacking faults in addition to intentionally inserted heterointerfaces. They affect the electronic properties, introduce band offsets, and hence influence the conductivity and carrier lifetimes. Therefore, the overall objective of this project is to investigate the electronic properties of sidewall surfaces, defects, and interfaces with atomic resolution, and correlate them with conductivity and carrier lifetimes of III-V semiconductor NWs.In particular, we plan to investigate in a first step (i) the possible Fermi level pinning, the energetic position, and its physical origin at the sidewall surfaces of different III-V material compositions and for different polytypes, (ii) the interface states, band alignments and offsets, as well as band gaps near heterointerfaces, (iii) the electronic properties of planar defects and polytype insertions, and (iv) the interaction of the surface Fermi level pinning with internal junctions, interfaces, and defects. In a second step, these properties will be correlated with the conductivity and carrier lifetimes of NWs. The main objectives are to elucidate, how an extrinsic surface pinning, interfaces as well as planar defects, and intentionally incorporated point defects affect conductivity and carrier lifetimes of NWs.