Intrinsically Linear Incremental Sigma-Delta Converters - iLIDS

增量σ - δ模数转换器（I-SD ADC）结合了两个世界的优点。它们依赖于过采样和噪声整形，它们仍然作为真正的奈奎斯特速率转换器，因此可以时间交错或多路复用。这是通过定期重置来实现的。虽然I-SD ADC在过去已经实现了非常高的分辨率，但非常低的速度，例如传感器接口，但最近已经展示了更高带宽的转换器，它还采用了更节能的连续时间（CT）实现环路滤波器。为了实现更高的带宽，必须实现内部多比特量化，因为必须降低过采样比（OSR）。多比特量化同时允许更稳定的系统运行，更积极的环路滤波器缩放，更多的最大稳定幅度（MSA）和对放大器的更少的动态要求。但在反馈式数模转换器（DAC）中存在着非线性的巨大缺点。在第一个项目阶段，我们提出了一种架构，即I-SMASH，它允许多位操作和DAC，同时通过动态重新配置操作不会受到DAC非线性的影响。介绍了FIR dac的应用，并对ISI进行了分析。原型实现可以显著地发布。然而，它也有缺点，稳定性、MSA、抖动和码间干扰（ISI）灵敏度是在第一个单比特相位定义的，而在第二个多比特相位只有利地定义了量化噪声性能。在提交的项目建议书中，我们希望扩展第一阶段的研究结果。采用本质线性5电平开关电容（SC） DAC，分析了CT环路滤波运算和放大器有限带宽的影响。它被修改为允许低动态和低灵敏度的抖动和ISI。我们将采用SC DAC的变体来实现这一目标。时间交错以实现更多电平，电流饥饿以降低峰值电流，FIR DAC实现以进一步降低动态。此外，该项目将通过采用基于噪声耦合SAR的内部量化来扩展先前的工作，以便在I-SMASH的两个阶段进行高阶环路滤波。最后，将修改分数排序的概念，以便能够将其与COI重构滤波器一起应用于动态重新配置的I-SD ADC。分数排序，一般形式的斩波，因此将允许减少低频噪声的影响，以及消除偏移。

Incremental Sigma-Delta Analog-digital Converters (I-SD ADC) combine the advantages of two worlds. They rely on oversampling and noise-shaping, and still they serve as true Nyquist rate converters and can thus be time-interleaved or multiplexed. This is achieved with a periodic reset.While I-SD ADC have been implemented in the past for very high resolution, but very low speed e.g. sensor interfaces, more recently higher bandwidth converters have been shown, which also employ the more power efficient continuous-time (CT) implementation of the loop filter. In order to achieve even higher bandwidth, a realization of internal multibit quantization comes as a necessity, as oversampling ratio (OSR) must be reduced. Multibit quantization concurrently allows more stable system operation, more aggressive loop filter scaling, more maximum stable amplitude (MSA) and less dynamic requirements on the amplifiers. But it comes with the tremendous disadvantage of non-linearity in the feedback digital-analog converter (DAC). In a first project phase, we have proposed an architecture, the I-SMASH, which allows multibit operation and DAC while not suffering from DAC non-linearity by dynamically reconfiguring the operation. Also, the employment of FIR DACs was introduced and ISI analyzed. A prototype implementation could be prominently published. Though, it came with the disadvantage, that stability, MSA, jitter and intersymbol interference (ISI) sensitivity are defined in the first, single-bit phase, whereas only the quantization noise performance is advantageously defined in the 2nd multibit phase.In the presented project proposal, we want to extend the findings of the first phase. An intrinsically linear 5-level switched capacitor (SC) DAC shall be employed, which is analyzed under the influence of CT loop filter operation and finite bandwidth of the amplifiers. It is modified to allow low dynamics and low sensitivity to jitter and ISI. We will employ variants of the SC DAC to achieve this. Time interleaving to achieve more levels, current starving to reduce peak currents, FIR DAC implementation to reduce dynamics further. Additionally, the project will extent the prior work by employing noise coupled SAR based internal quantization, in order to allow higher order loop filtering in both stages of I-SMASH. Finally, the concept of fractional sequencing will be modified to be able to employ it in dynamically reconfigured I-SD ADC together with COI reconstruction filters. Fractional sequencing, a general form of chopping, will thereby allow to reduce the influence of low frequency noise as well as to eliminate offset.