0-X MASH Continuous-Time Pipeline ADC based on TI-SAR

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Continuous-time (CT) Analog-to-Digital Converters (ADC) offer great advantages concerning speed, drivability and power efficiency. One very promising architecture is the so-called CT pipeline ADC, which can be implemented as a 0-X MASH Delta-Sigma Modulator. In the state of the art, the coarse quantizer is realized with low resolution Successive Approximation Register (SAR) ADCC, which serves to build a residue, which goes through an interstage gain (ISG) and a fine ADCF that is realized as a CT DSM. The low resolution of ADCC yields larger residue, which again limits the ISG, which again puts more stringent requirements to the fine ADCF. Moreover, the coarse DACC, which is used to build the residue, has low resolution, but needs the full linearity of the overall CT pipeline ADC. The state of the art employs digital calibration of mostly undisclosed complexity. The first project phase intended to investigate the possibility to include time-interleaved (TI) quantization by means of TI-SAR to implement MASH DSM ADC. A solution was found for an intrinsically linear DACC, which is realized using a digital DSM (DDSM). Thereby, the coarse ADCC can be implemented by a TI-SAR, whose TI-output is fed into a single linear DACC, avoiding any TI non-idealities. An advance state-of-the-art TI SAR was implemented in a 22nm CMOS process. Further research was performed on the required allpass filter for residue building and the requirements on the digital cancellation logic. In the second project phase, the found DDSM based DACC must be realized in an as little complexity as possible implementation in order to allow GHz-operation. The optimal location of ISG will be investigated and its interdependency with the out-of-band quantization noise of the DDSM will be analyzed. We aim for a full implementation of this novel CT pipeline ADC based on the TI-SAR coarse quantizer, the innovative DDSM coarse DACC and a reduced complexity digital cancellation logic.