0-X MASH Continuous-Time Pipeline ADC based on TI-SAR

基于 TI-SAR 的 0-X MASH 连续时间流水线 ADC

基本信息

项目摘要

Continuous-time (CT) Analog-to-Digital Converters (ADC) offer great advantages concerning speed, drivability and power efficiency. One very promising architecture is the so-called CT pipeline ADC, which can be implemented as a 0-X MASH Delta-Sigma Modulator. In the state of the art, the coarse quantizer is realized with low resolution Successive Approximation Register (SAR) ADCC, which serves to build a residue, which goes through an interstage gain (ISG) and a fine ADCF that is realized as a CT DSM. The low resolution of ADCC yields larger residue, which again limits the ISG, which again puts more stringent requirements to the fine ADCF. Moreover, the coarse DACC, which is used to build the residue, has low resolution, but needs the full linearity of the overall CT pipeline ADC. The state of the art employs digital calibration of mostly undisclosed complexity. The first project phase intended to investigate the possibility to include time-interleaved (TI) quantization by means of TI-SAR to implement MASH DSM ADC. A solution was found for an intrinsically linear DACC, which is realized using a digital DSM (DDSM). Thereby, the coarse ADCC can be implemented by a TI-SAR, whose TI-output is fed into a single linear DACC, avoiding any TI non-idealities. An advance state-of-the-art TI SAR was implemented in a 22nm CMOS process. Further research was performed on the required allpass filter for residue building and the requirements on the digital cancellation logic. In the second project phase, the found DDSM based DACC must be realized in an as little complexity as possible implementation in order to allow GHz-operation. The optimal location of ISG will be investigated and its interdependency with the out-of-band quantization noise of the DDSM will be analyzed. We aim for a full implementation of this novel CT pipeline ADC based on the TI-SAR coarse quantizer, the innovative DDSM coarse DACC and a reduced complexity digital cancellation logic.
连续时间(CT)模数转换器(ADC)在速度、可驱动性和功率效率方面具有很大的优势。一种非常有前途的结构是所谓的CT流水线ADC,它可以实现为0-X MASH Delta-Sigma调制器。在现有技术中,粗量化器是用低分辨率逐次逼近寄存器(SAR)ADCC来实现的,该ADCC用于构建余数,该余数经过级间增益(ISG)和被实现为CT DSM的精细ADCF。ADCC的低分辨率产生了更大的残留物,这再次限制了ISG,这再次对精细的ADCF提出了更严格的要求。此外,用于构建残差的粗略DACC分辨率较低,但需要整个CT流水线ADC的完全线性。最先进的技术采用了数字校准,其复杂性大多不为人知。第一个项目阶段旨在研究利用时间交错(TI)合成孔径雷达进行时间交错(TI)量化以实现MASH DSM ADC的可能性。找到了一种用数字DSM(DDSM)实现的本征线性DACC的解决方案。因此,粗略的ADCC可以由TI-SAR实现,其TI输出被馈送到单个线性DACC,避免了任何TI非理想情况。一种先进的TI合成孔径雷达采用了22 nm的CMOS工艺实现。对余数形成所需的全通滤波器和对数字抵消逻辑的要求进行了进一步研究。在第二个项目阶段,必须以尽可能低的实现复杂度来实现所找到的基于DDSM的DACC,以便允许GHz操作。对ISG的最佳位置进行了研究,并分析了其与DDSM的带外量化噪声的相关性。我们的目标是基于TI-SAR粗量化器、创新的DDSM粗略DACC和降低复杂度的数字对消逻辑来完全实现这种新型CT流水线ADC。

项目成果

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Professor Dr.-Ing. Maurits Ortmanns其他文献

Professor Dr.-Ing. Maurits Ortmanns的其他文献

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{{ truncateString('Professor Dr.-Ing. Maurits Ortmanns', 18)}}的其他基金

Implantable module-based microchip networks
基于可植入模块的微芯片网络
  • 批准号:
    401023906
  • 财政年份:
    2018
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Single OpAmp Higher-Order Filters in Sigma-Delta Modulators
Sigma-Delta 调制器中的单运算放大器高阶滤波器
  • 批准号:
    334873694
  • 财政年份:
    2017
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Highest-Linearity Nyquist Rate SAR ADCs in nm-CMOS - NanoSAR
采用 nm-CMOS 的最高线性奈奎斯特速率 SAR ADC - NanoSAR
  • 批准号:
    245868713
  • 财政年份:
    2014
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Effective data reduction for wireless transmission of neural activity (EDnA)
有效减少神经活动无线传输的数据 (EDnA)
  • 批准号:
    230027621
  • 财政年份:
    2013
  • 资助金额:
    --
  • 项目类别:
    Research Grants
State- and parameter estimation in Sigma-Delta ADC`s by using Kalman-filters
使用卡尔曼滤波器估计 Sigma-Delta ADC 中的状态和参数
  • 批准号:
    190715610
  • 财政年份:
    2011
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Korrelationsbasierte Systemanalyse und Hintergrund-Korrektur für Sigma-Delta Analog-Digital Umsetzer durch Nutzung optimaler Testsignale
使用最佳测试信号对 Sigma-Delta 模数转换器进行基于相关性的系统分析和背景校正
  • 批准号:
    40403750
  • 财政年份:
    2007
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Dual Quantization DAC for High-Linearity Multibit Continuous-Time Sigma-Delta Modulators - DuQDAC
用于高线性度多位连续时间 Sigma-Delta 调制器的双量化 DAC - DuQDAC
  • 批准号:
    433735880
  • 财政年份:
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Intrinsically Linear Incremental Sigma-Delta Converters - iLIDS
本质线性增量 Sigma-Delta 转换器 - iLIDS
  • 批准号:
    390567189
  • 财政年份:
  • 资助金额:
    --
  • 项目类别:
    Research Grants
Secure Mixed-Signal Neural Networks - SeMSiNN
安全混合信号神经网络 - SeMSiNN
  • 批准号:
    535473873
  • 财政年份:
  • 资助金额:
    --
  • 项目类别:
    Priority Programmes
Time-Variant Architectures and Stabilty Criteria for Incremental Sigma-Delta ADC(TASC for IADC )
增量 Sigma-Delta ADC 的时变架构和稳定性标准(TASC for IADC)
  • 批准号:
    288845960
  • 财政年份:
  • 资助金额:
    --
  • 项目类别:
    Research Grants

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