Time-Variant Architectures and Stabilty Criteria for Incremental Sigma-Delta ADC(TASC for IADC )

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The proposed research project aims towards a systematic design process for incremental sigma-delta A/D converters. This type of A/D converter shows particular potential in the prior art, especially with small to moderate conversion rates and very high resolutions; Recent work shows that completely new, fast ADCs can work on the principle of incremental ADCs. However, previous design approaches are limited to empirical design rules, mostly apply the knowledge of continuously working, normal sigma-delta converters, do not have the option of including non-idealities, and therefore do not offer the possibility of a systematic design process. In preliminary work it was e.g. shown that this type of ADC has the potential to use time-variant architectures with time-dependent non-idealities due to the incremental working method. Low non-idealities at the beginning and high non-idealities at the end of an implementation cycle allow performance to be saved with almost the same level of performance. However, the design process for such time-variant architectures and their optimization compared to time-variant non- idealities has not yet been fully researched. In addition, the incremental sigma-delta modulator (implemented with a continuous- time loop filter) is a time- varying, mixed discrete-continuous-time system that is highly non- linear due to the internal quantization. Although many analysis methods for the stability behavior of free- running sigma-delta modulators have been described, only the simplest variant is often used in practice, which has often been shown in simulations to be unsuitable for incremental ADC. For this reason, this research project will focus not only on the optimal design process for time-variant architectures of incremental converters and the inclusion of time- variant non-idealities therein, but also on their stability behavior. Stability metrics are applied for the incremental mode of operation and compared to the usual ad-hoc metrics of free running modulators. The intention is to significantly improve the design process and ultimately the power efficiency for the circuit design of incremental Sigma Delta converters.