0-X MASH Continuous-Time Pipeline ADC based on TI-SAR

连续时间（CT）模数转换器（ADC）在速度、驾驶性能和功率效率方面具有很大的优势。一个非常有前途的架构是所谓的CT流水线ADC，它可以实现为0-X MASH Delta-Sigma调制器。目前，粗量化器是用低分辨率逐次逼近寄存器（SAR） ADCC实现的，该ADCC用于构建残差，残差通过级间增益（ISG）和精细ADCF实现为CT DSM。ADCC的低分辨率产生较大的残留物，这再次限制了ISG，这再次对精细ADCF提出了更严格的要求。此外，用于构建残差的粗DACC分辨率较低，但需要整体CT流水线ADC的全线性度。最先进的技术采用了大多数未公开复杂性的数字校准。第一个项目阶段旨在研究通过TI- sar包括时间交错（TI）量化的可能性，以实现MASH DSM ADC。提出了一种利用数字DSM （DDSM）实现本质线性DACC的方法。因此，粗ADCC可以通过TI- sar实现，其TI输出被馈送到单个线性DACC，避免任何TI非理想性。在22nm CMOS工艺中实现了先进的最先进的TI SAR。进一步研究了残差构建所需的全通滤波器和数字对消逻辑的要求。在第二个项目阶段，所发现的基于DDSM的DACC必须以尽可能低的复杂性实现，以便允许ghz操作。研究了ISG的最佳位置，并分析了其与DDSM带外量化噪声的相互关系。我们的目标是完全实现这种基于TI-SAR粗量化器、创新的DDSM粗DACC和降低复杂性的数字对消逻辑的新型CT流水线ADC。

Continuous-time (CT) Analog-to-Digital Converters (ADC) offer great advantages concerning speed, drivability and power efficiency. One very promising architecture is the so-called CT pipeline ADC, which can be implemented as a 0-X MASH Delta-Sigma Modulator. In the state of the art, the coarse quantizer is realized with low resolution Successive Approximation Register (SAR) ADCC, which serves to build a residue, which goes through an interstage gain (ISG) and a fine ADCF that is realized as a CT DSM. The low resolution of ADCC yields larger residue, which again limits the ISG, which again puts more stringent requirements to the fine ADCF. Moreover, the coarse DACC, which is used to build the residue, has low resolution, but needs the full linearity of the overall CT pipeline ADC. The state of the art employs digital calibration of mostly undisclosed complexity. The first project phase intended to investigate the possibility to include time-interleaved (TI) quantization by means of TI-SAR to implement MASH DSM ADC. A solution was found for an intrinsically linear DACC, which is realized using a digital DSM (DDSM). Thereby, the coarse ADCC can be implemented by a TI-SAR, whose TI-output is fed into a single linear DACC, avoiding any TI non-idealities. An advance state-of-the-art TI SAR was implemented in a 22nm CMOS process. Further research was performed on the required allpass filter for residue building and the requirements on the digital cancellation logic. In the second project phase, the found DDSM based DACC must be realized in an as little complexity as possible implementation in order to allow GHz-operation. The optimal location of ISG will be investigated and its interdependency with the out-of-band quantization noise of the DDSM will be analyzed. We aim for a full implementation of this novel CT pipeline ADC based on the TI-SAR coarse quantizer, the innovative DDSM coarse DACC and a reduced complexity digital cancellation logic.