Intrinsically Linear Incremental Sigma-Delta Converters - iLIDS

本质线性增量 Sigma-Delta 转换器 - iLIDS

• 批准号: 390567189
• 负责人: Professor Dr.-Ing. Maurits Ortmanns
• 金额: --
• 依托单位: Institut für Mikroelektronik (Mikro)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/390567189?language=en
• 关键词: Intrinsically; Linear; Incremental; Sigma; Delta

Incremental Sigma-Delta Analog-digital Converters (I-SD ADC) combine the advantages of two worlds. They rely on oversampling and noise-shaping, and still they serve as true Nyquist rate converters and can thus be time-interleaved or multiplexed. This is achieved with a periodic reset.While I-SD ADC have been implemented in the past for very high resolution, but very low speed e.g. sensor interfaces, more recently higher bandwidth converters have been shown, which also employ the more power efficient continuous-time (CT) implementation of the loop filter. In order to achieve even higher bandwidth, a realization of internal multibit quantization comes as a necessity, as oversampling ratio (OSR) must be reduced. Multibit quantization concurrently allows more stable system operation, more aggressive loop filter scaling, more maximum stable amplitude (MSA) and less dynamic requirements on the amplifiers. But it comes with the tremendous disadvantage of non-linearity in the feedback digital-analog converter (DAC). In a first project phase, we have proposed an architecture, the I-SMASH, which allows multibit operation and DAC while not suffering from DAC non-linearity by dynamically reconfiguring the operation. Also, the employment of FIR DACs was introduced and ISI analyzed. A prototype implementation could be prominently published. Though, it came with the disadvantage, that stability, MSA, jitter and intersymbol interference (ISI) sensitivity are defined in the first, single-bit phase, whereas only the quantization noise performance is advantageously defined in the 2nd multibit phase.In the presented project proposal, we want to extend the findings of the first phase. An intrinsically linear 5-level switched capacitor (SC) DAC shall be employed, which is analyzed under the influence of CT loop filter operation and finite bandwidth of the amplifiers. It is modified to allow low dynamics and low sensitivity to jitter and ISI. We will employ variants of the SC DAC to achieve this. Time interleaving to achieve more levels, current starving to reduce peak currents, FIR DAC implementation to reduce dynamics further. Additionally, the project will extent the prior work by employing noise coupled SAR based internal quantization, in order to allow higher order loop filtering in both stages of I-SMASH. Finally, the concept of fractional sequencing will be modified to be able to employ it in dynamically reconfigured I-SD ADC together with COI reconstruction filters. Fractional sequencing, a general form of chopping, will thereby allow to reduce the influence of low frequency noise as well as to eliminate offset.

增量Sigma-Delta模数转换器(I-SD ADC)结合了两个领域的优势。它们依靠过采样和噪声整形，仍然充当真正的奈奎斯特速率转换器，因此可以进行时间交织或多路复用。这是通过定期重置来实现的。虽然I-SD ADC过去实现的是非常高的分辨率，但速度非常低，例如传感器接口，但最近出现了更高带宽的转换器，它也采用了更省电的连续时间(CT)环路滤波器实现。为了获得更高的带宽，必须实现内部多比特量化，因为必须降低过采样率(OSR)。多位量化同时允许更稳定的系统操作、更积极的环路滤波器缩放、更大的最大稳定幅度(MSA)和对放大器的更低动态要求。但是，反馈数模转换器(DAC)存在着非线性的巨大缺点。在第一个项目阶段，我们提出了一个架构，I-SMASH，它允许多位运算和DAC，同时通过动态重新配置操作而不受DAC非线性的影响。介绍了FIR数模转换器的应用，并对码间干扰进行了分析。原型实现可能会在显著位置发布。然而，它的缺点是，稳定性、MSA、抖动和符号间干扰(ISI)敏感性在第一个单比特阶段被定义，而在第二个多比特阶段仅定义量化噪声性能是有利的。采用本征线性的5电平开关电容(SC)DAC，分析了CT环路滤波操作和放大器带宽有限的影响。它被修改为允许低动态和对抖动和ISI的低敏感度。我们将采用SC DAC的变种来实现这一点。时间交错实现更多的电平，电流饥饿降低峰值电流，FIR DAC实现进一步降低动态。此外，该项目将通过采用基于噪声耦合的SAR的内部量化来扩展先前的工作，以便在I-SMASH的两个阶段都允许更高阶的环路滤波。最后，分数排序的概念将被修改，以便能够将其与COI重建滤波器一起用于动态重新配置的I-SD ADC。分数排序是斩波的一种一般形式，因此可以减少低频噪声的影响并消除偏移。