Fast and Accurate Design Methodologies using Fully Event-Driven Simulations for non-ideal Mixed-Signal Systems

当今无线通信变得越来越重要，需要高功率效率和高密度的IC的实现。因此，DC-DC转换器或锁相环（PLL）等混合信号系统的集成度越来越高。这些系统混合了模拟和数字部分，并表现出非线性脉宽调制（PWM）开关行为。因此，它们的设计不能依赖于一般的反馈理论，并且通常使用晶体管或行为水平的模拟。晶体管级（TL）模型非常准确，而行为模型更容易处理寄生效应。这些方法的主要瓶颈是长的处理时间，巨大的计算消耗和总体设计成本。因此，快速洞察系统的行为是困难的，危及一个强大的设计的保证。此外，TL同时考虑所有非理想效应，这使得分析它们对性能的单一和组合影响变得更加复杂。为了快速了解系统特性，使用基于线性模型的设计方法。由于采用了早期线性化方法，不考虑非线性和非理想效应。然而，考虑它们对于鲁棒设计至关重要，因为它们影响稳定性、频率纯度和瞬态动态行为。此外，这些建模方法的有效性是有限的域接近的操作点，丢弃它们的瞬态拉在预测是必不可少的，当考虑频率synthesization.To联合收割机的TL模拟和线性模型的效率的准确性，混合信号系统可以表示由事件驱动（艾德）建模方法。以电荷泵锁相环为例，介绍了一种考虑主要非理想效应的艾德模型。该模型仅评估PWM过程的触发沿，从而大幅减少了仿真时间和生成的数据量。加速因子高达100000，预计与TL simulation.In这个项目中，以克服混合信号系统的设计挑战，即开关行为，非理想和非线性行为，高效的艾德模型将先进的CP锁相环，时钟和数据恢复锁相环和延迟锁定环的应用。所有主要寄生效应和非线性效应将在TL提取，并在艾德表示中建模。此外，将实现艾德模型和Cadence之间的接口，以实现实用的参数提取。一旦艾德模型被这些寄生效应所丰富，它们对环路性能的影响将被系统地探索，从而导致混合信号PLL和DLL的详尽且更鲁棒的设计方法。为了证明这种建模和设计方法的可行性，收集的知识将外推到其他混合信号系统，如DC-DC转换器。

Nowadays wireless communication is becoming more important and need the implementation of power efficient and high density ICs. Hence, mixed-signal systems like DC-DC converters or phase-locked loops (PLL) are increasingly integrated.These systems mix analogue and digital parts and exhibit a nonlinear pulse-width modulated (PWM) switching behaviour. Thus their design cannot rely on general feed-back theories and simulations at transistor or behavioural levels are often used. Transistor-level (TL) models are very accurate, whereas behavioural models allow an easier handling of parasitic effects. The main bottlenecks of these approaches are the long processing times, the huge computational consumption and the overall design costs. Thus a quick insight into the system behaviour is made difficult endangering the guaranty of a robust design. In addition, at TL all non-ideal effects are considered at once, making the analysis of their singular and combined influences on the performances even more complex.To get a quick overview of the system properties, design methods based on linear models are used. Because of the early linearization, nonlinear and non-ideal effects are not considered. However, it is crucial to take them into account for a robust design, since they affect the stability, frequency purity and transient dynamic behaviour. Additionally, the validity of these modelling approaches is limited to the domain close to the operation point, discarding them for transient pull-in predictions which are essential when considering frequency synthesis.To combine the accuracy of TL simulations and the efficiency of linear models, a mixed-signal system can be represented by an event-driven (ED) modelling approach. Based on the example of a charge pump (CP) PLL, an ED model considering the major non-ideal effects is introduced here. This model evaluates only the triggering edges of the PWM procedure, reducing drastically the simulation time and the amount of produced data. Speed-up factors up to 100000 are expected with a very good accuracy compared to TL simulations.In this project, to overcome the design challenges of mixed-signal systems, i.e. switching behaviour, non-ideal and nonlinear behaviour, the efficient ED model will be advanced to cover the CP-PLL, clock and data recovery PLL and Delay-Locked Loop applications. All major parasitic and nonlinear effects will be extracted at TL and modelled within the ED representation. In addition, an interface between the ED model and Cadence will be implemented in order to realise a practical parameter extraction. Once the ED model is enriched by these parasitic effects, their influence on the loop performances will be systematically explored, leading to an exhaustive and more robust design methodology of mixed-signal PLLs and DLLs. To show the feasibility of this modelling and design methodology, the gathered knowledge will be extrapolated to other mixed-signal systems like the DC-DC converter.