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Self-Aligned Short Channel Complementary Field Effect Transistors on Transparent Substrates (SACFETTS)

透明基板上的自对准短沟道互补场效应晶体管 (SACFETTS)

基本信息

批准号：
318540667
负责人：
Professor Dr.-Ing. Ulrich Hilleringmann
金额：
--
依托单位：
Institut für Elektrotechnik und Informationstechnik
依托单位国家：
德国
项目类别：
Research Grants
财政年份：
2016
资助国家：
德国
起止时间：
2015-12-31 至 2018-12-31
项目状态：
已结题

来源：
https://gepris.dfg.de/gepris/projekt/318540667?language=en
关键词：
Self Aligned Short Channel Complementary

项目摘要

Based on p-type organic and n-type ZnO- thin-film transistors on transparent substrates an advanced complementary transistor integration technique with short channel capability will be developed and analyzed. A shrink in the transistor channel length and a reduction of the parasitic capacitances from the gate to the drain/source contacts by self-alignment will shrink the delay time and will improve the RF-characteristics of these FETs. Additionally a transfer from ZnO to ZnO/SnO2 nanoparticle films and an application of DNTT or C8-BTBT will raise the transistors charge carrier mobilities into the >10 cm2/(Vs) range. This will enable electronics for high frequencies of some tenth of MHz at a low production cost level. Main requests for processing of the devices are: - Self-alignment of the gate structures by special UV light exposure technique - Extension of the technique into the sub-µm range - Introduction of a suitable gate dielectric layer and analysis on the transistors cut-off frequency - A common metallization for both types of transistors including contact resistance analysis - Compensation of instability effects due to traps and interface states - Quality and parameter analysis: Comparison of standard and self-aligned transistors with inverted coplanar and inverted staggered device setups - Complementary inverter setups with self-aligned transistors in comparison to standard transistors For further developments attention will be paid to low temperature processing and ink jet printing capability for the applied layers

基于透明衬底上的p型有机和n型ZnO薄膜晶体管，将开发和分析具有短沟道能力的先进互补晶体管集成技术。晶体管沟道长度的收缩以及通过自对准减小从栅极到漏极/源极接触的寄生电容将缩短延迟时间并且将改善这些FET的RF特性。此外，从ZnO到ZnO/SnO 2纳米颗粒膜的转移以及DNTT或C8-BTBT的应用将使晶体管的电荷载流子迁移率提高到>10 cm 2/（Vs）的范围。这将使电子产品能够以低生产成本水平用于大约十分之一MHz的高频。器械处理的主要请求包括：- 通过特殊的紫外线曝光技术实现栅极结构的自对准-将该技术扩展到亚微米范围-引入合适的栅极介电层并分析晶体管截止频率-两种类型晶体管的通用金属化，包括接触电阻分析-补偿陷阱和界面态引起的不稳定性效应-质量和参数分析：标准和自对准晶体管与反向共面和反向交错器件设置的比较-互补反相器设置与自对准晶体管与标准晶体管的比较对于进一步的开发，将关注应用层的低温处理和喷墨打印能力