phySicAlly secUre reconfiguraBlE platfoRm (SAUBER)

在日益增长的数字世界中，日常生活的许多方面完全由信息技术基础设施完成，他们对安全的担忧比以往任何时候都更大。一方面，软件变得更加安全，另一方面，硬件变得更容易妥协，硬件成为系统安全的致命弱点。在当今复杂的片上系统(SoCS)中，以现场可编程门阵列(现场可编程门阵列)为形式的可重构结构因其快速上市、灵活性和可更新性而发挥着重要的作用。现场可编程门阵列对于许多安全平台也是非常有前景的，因为它们允许对硬件和系统进行“安全补丁”，就像通常通过软件完成的那样。尽管现场可编程门阵列在安全应用方面有着如此广阔的前景，但由于现有的商业可重构技术并不是为安全应用而设计的，因此仍有许多安全问题需要解决。由于高面积、低吞吐量、高功率/能量、高延迟等特点，目前已知的抗物理攻击措施在现场可编程门阵列平台上的应用存在挑战，这种安全方案的实现和映射到现场可编程门阵列上是“自组织的”，这意味着对于每一种密码算法和每一种设计体系结构，对抗措施都需要重新调整。此外，现有的FPGA技术容易受到多种安全攻击和旁路分析，甚至使攻击者能够远程攻击系统。本项目的主要目标是设计一个安全的可重构平台(SAUBER)，该平台可以抵抗各种恶意的物理攻击，并可以作为SoC中的信任中心，以实现密码算法等高度安全的功能。新平台将提供针对侧通道分析攻击、故障注入攻击、热攻击、电源噪声攻击的强大保护，同时支持针对物理攻击的算法对策所需的可调整安全原语，例如PRNG。我们将研究如何采用和重新设计现有的基于ASIC的隐藏对策，以便它们在可重构平台上的实现将导致对物理攻击的强大保护。我们将在现有开源FPGA映射工具的基础上，设计安全可重构结构，开发安全映射工具链，将用户应用自动映射到该平台，并以系统化和自动化的方式嵌入安全功能。

In the growing digital world, where many aspects of daily life are solely performed by the information technology infrastructure, their security concerns are greater than ever before. With software becoming more secure on one hand, and compromising hardware becoming easier on the other hand, the hardware becomes the Achilles heel for the system security. In complex systems on chip (SoCs) of today, the reconfigurable fabric, in the form of field programmable gate array (FPGA), plays an important role due to its rapid time to market, flexibility, and updatability. FPGAs are also very promising for many secure platforms, since they allow “security patches” to the hardware and the system, as it is normally done in software. Despite such promising prospects of FPGAs for secure applications, there are still many security issues to be resolved for the FPGA fabric since the existing commercially-available reconfigurable technology is not made for secure applications. There exist challenges in applying the currently-known countermeasures to physical attacks in FPGA platforms, due to high area, low throughput, high power/energy, high latency, etc. The implementation and mapping of such security schemes to the FPGA is “ad hoc”, meaning for every cryptographic algorithm and every design architecture, the countermeasures should be readjusted. In addition, the existing FPGA technology is vulnerable to many security attacks and side-channel analysis, even enabling adversaries to attack the system remotely.The main objective of this project is to design a secure reconfigurable platform (SAUBER), which is resilient to various malicious physical attacks and can act as the center of trust in SoCs, in order to implement cryptographic algorithms and other highly secure functions. The new platform would provide strong protection against side-channel analysis attacks, fault-injection attacks, thermal attacks, power supply noise attacks and at the same time enable adjustable security primitives, e.g., PRNG, necessary for algorithmic countermeasures against physical attacks. We will investigate how to adopt and re-design currently available ASIC-based hiding countermeasures so that their realization in a reconfigurable platform would lead to strong protection against physical attacks. We will design the secure reconfigurable fabric and develop the secure mapping toolchain, on top of existing open source FPGA mapping tools, to automatically map user applications to this platform and embed security features in a systematic and automated manner.