SSIMA – Scalable Side-Channel Immune Micro-Architecture

本研究的重点是解决当前嵌入式微架构在提供针对被动和主动物理攻击的综合保护方面的局限性，例如侧通道分析（SCA）和故障注入（FI）。我们的目标是探索可组合架构的构造，这些架构可以在组合设置中维护针对这些攻击的安全性。该研究旨在实现构建这些体系结构的可伸缩性，允许使用单个硬件设计以任意顺序实现SCA安全性。主要目标是开发使用定制嵌入式平台的可扩展物理安全软件的方法，而不会出现微架构泄漏。可伸缩性涉及使实现适应不同的对手模型和容错需求，同时保持理论和实践的安全保证。计划设计和开发RISC-V平台，包括相应的指令集架构（ISA）和专用指令集扩展（ISE），使软件设计人员能够毫不费力地将用高级语言（例如C语言）编写的未受保护的软件转换为开发平台的机器码。最终的实现应该提供针对已定义的对手的安全性，同时在实践中支持理论上的安全性参数。成功的结果将代表isa开发的重大进步，具有执行任意软件的可证明的安全性。

This research focuses on addressing the limitations of current embedded micro-architectures in providing comprehensive protection against combined passive and active physical attacks, such as side-channel analysis (SCA) and fault injection (FI). The objective is to explore the construction of composable architectures that can maintain security against these attacks in a combined setting. The study aims to achieve scalability in constructing these architectures, allowing for SCA security at arbitrary orders using a single hardware design. The primary objective is to develop methodologies for scalable physically secure software using customized embedded platforms without micro-architectural leakage. Scalability involves adapting implementations to different adversary models and fault tolerance requirements while maintaining theoretical and practical security guarantees. It is planned to design and develop a RISC-V platform, including the corresponding instruction set architecture (ISA) and dedicated Instruction Set Extensions (ISE), that enables software designers to effortlessly convert unprotected software written in high-level languages (e.g., C) into machine code for the developed platform. The resulting implementation should provide security against defined adversaries while upholding theoretical security arguments in practice. The successful outcome would represent a significant advancement in the development of ISAs with provable security for executing arbitrary software.