NaSCA: Nano-Scale Side-Channel Analysis - Physical Security for Next-Generation CMOS ICs

目前，我们正被越来越多的网络物理系统所包围，例如电子收费、交通管理、电子支付、智能家居等。尽管这提供了许多好处，但嵌入式安全设备是由合法用户控制的，合法用户可以扮演攻击者的角色。它带来了系统安全方面的严重风险，而不仅仅是由于加密算法的缺陷。此外，作为普遍应用程序的严重威胁，实现攻击可以将理论上健壮的系统变成一个完全崩溃的设置。正如许多侧信道分析（SCA）攻击所证明的那样，保护无处不在的系统是必须的，也是一项重要的任务。有趣的是，SCA社区提供了一个大型的高级对策工具箱，用于保护加密设备免受此类物理攻击。基于动态功耗原理，设计了功率分析对策。然而，随着技术的快速发展，缩小纳米级CMOS电路的静态功耗已成为人们关注的主要问题。因此，当SCA对手考虑静态功耗时，已知的对策存在严重缺陷。在不久的将来，配备了理论上合理的对策的加密设备将无法提供所需的保护水平，因为它们的安全性是可以证明的，不包括静态功率的概念。事实上，我们在该领域的初步研究结果（通过静态电源检查FPGA平台的SCA漏洞）支持这一说法。然而，考虑到动态和静态功率，开发保护解决方案将是非常有益的。我们相信，至少在一定程度上，通过仔细地重新设计、扩展和组合已知的对策，这是可能的。在这个项目中，我们将通过FPGA和ASIC平台的静态电源研究SCA。我们将分析保护加密设备（例如AES协处理器）免受静态功率分析攻击的已知对策的效率。在此基础上，将（重新）设计对策以匹配某些需求，从而产生具有增强功能的更健壮的方案。我们将根据实际分析结果开发专用且可证明安全的对策（适用于FPGA和ASIC平台）。制作的ASIC样品和FPGA模块将进行实际评估，以确保我们开发的对策的鲁棒性。因此，需要基于应用密码学和密码工程的跨学科努力来应对这些挑战。与我们的方法相反，以前的工作通常只处理动态功率侧通道，使用启发式物理安全技术或基本混淆方案，并且缺乏可靠的证据来证明安全性。事实上，SCA社区几乎没有考虑过通过静态电源抵抗SCA攻击。

Currently we are being surrounded by an ever-growing number of cyber-physical systems e.g., electronic toll collection, traffic management, electronic payments, smart homes etc. Although this offers many benefits, the embedded security-enabled devices are in control of legitimate users, who can play the role of an adversary. It enables serious risks with respect to system security, not only due to the flaws of crypto algorithms. Also, the implementation attacks, as serious threats for pervasive applications, can turn a theoretically-robust system into a completely-broken setup. As demonstrated by numerous side-channel analysis (SCA) attacks, securing ubiquitous systems is a must as well as a non-trivial task. Interestingly, the SCA community offers a large toolbox of advanced countermeasures for protecting the crypto devices against such physical attacks. The power analysis countermeasures have been designed based on the principle of dynamic power consumption. However, by fast technology shrinking static power consumption of nano-scale CMOS circuits is becoming a major concern. Hence, the known countermeasures have serious shortcomings when static power consumption is considered by an SCA adversary. In the near future the cryptographic devices, equipped with theoretically-sound countermeasures, will fail to provide the desired level of protection as their security is provable excluding the concept of static power. Indeed, the result of our preliminary study in this area, where we examined the SCA vulnerability of FPGA platforms through static power, supports this statement. Nevertheless, it would be a great benefit to develop protection solutions considering both dynamic and static power. We believe that this is possible, at least to a certain extent, by carefully re-designing, extending, and composing the known countermeasures. In this project we will investigate SCA through static power for FPGA and ASIC platforms. We will analyze the efficiency of the known countermeasures to protect crypto devices (e.g., an AES coprocessor) against static power analysis attacks. Based on this, countermeasures will be (re-)designed to match the certain requirements resulting in more robust schemes with enhanced functionality. We will develop dedicated and provably-secure countermeasures (for FPGA and ASIC platforms) based on the result of our practical analyses. The fabricated ASIC samples and the FPGA modules will be practically evaluated to ensure the robustness of our developed countermeasures. Hence, an interdisciplinary effort based on applied cryptography and cryptographic engineering is required to cope with these challenges.In contrast to our approach, previous works usually deal with solely dynamic power side channel, use heuristic physical security techniques or basic obfuscation schemes, and lack sound proof to prove the security. In fact, resistance against SCA attacks through static power has barely been considered by the SCA community.