Technology-aware 3D interconnect architectures for heterogeneous SoCs manufactured in monolithic 3D integration

单片3D集成技术（M3D）是一种颠覆性的3D片上系统设计技术。与更传统的3D集成方案相比，M3D允许相邻层之间垂直互连的非常密集的集成。再加上外部的异质性，即不同电气特性的层的组合，为新的建筑设计和扩展系统功能提供了前所未有的机会。这些好处已经被许多研究处理元素和记忆的工作所证明；然而，对于片上通信架构，如片上网络，相关的工作却很少。此外，这些工作往往忽略了由单片制造引起的内在异质性的重大影响，例如与工艺相关的晶体管在较高层上的退化，较低层上的互连退化，或层之间路由资源的不均匀分布。最后，之前的作品主要是利用三维的线长缩减，而没有考虑延伸的微观和宏观建筑设计空间。我们希望通过分析单片3D集成的特性如何影响单个网络组件的微体系结构设计以及通信基础设施的体系结构来解决所有这些缺点。此外，我们将分析这些修改和扩展设计选项对整个系统架构的影响。该项目将为科学界提供四个具体贡献：1)它将为优化的3D互联架构提供系统的设计指南和一套架构模板，以解决外在和内在的异质性；2)将提供将片上网络拓扑综合作为优化问题制定的模型；3)提供支持系统设计空间探索的工具集，涵盖所有相关的M3D技术特征；4)本文将通过视觉片上系统和多处理器系统两个演示系统来展示优化潜力。该项目的主要成果将是更深入地了解如何利用单片3D集成的破坏性特征来改进3D集成电路中的互连架构。这允许优化系统的设计，不支持当前的设计概念。

Monolithic 3D integration (M3D) is a disruptive technology for the design of 3D System-on-Chips. In contrast to more conventional 3D integration schemes, M3D permits a very dense integration of vertical interconnects between neighboring tiers. Together with extrinsic heterogeneity, i.e., the combination of tiers with different electrical characteristics, unprecedented opportunities for new architectural designs and extended system functionalities arise. These benefits have been proven by numerous works addressing processing elements and memories; yet, for on-chip communication architectures such as Network-on-Chips, only few related works exist. Further on, these works often neglect the significant impact of intrinsic heterogeneity caused by monolithic fabrication, such as process-related transistor degradations on higher tiers, interconnect degradations on lower tiers, or the non-uniform distribution of routing resources among tiers. Finally, previous works primarily exploit wire length reduction in 3D, yet do not consider the extended micro- and macroarchitectural design space. We want to address all of these shortcomings by analyzing how the characteristics of monolithic 3D integration affect the design of the microarchitecture of individual network components, and the architecture of the communication infrastructure. Furthermore, we will analyze the impact of these modifications and extended design options on the overall system architecture. The project will provide four specific contributions to the scientific community: 1) It will provide systematic design guidelines and a set of architectural templates for optimized 3D interconnect architectures addressing extrinsic and intrinsic heterogeneity; 2) It will provide models for formulating Network-on-Chip topology synthesis as an optimization problem; 3) It will provide a toolset for supporting a systematic design space exploration, which accounts for all relevant M3D technology characteristics;4) It will demonstrate the optimization potential by means of two demonstrators, a Vision-System-on-Chip and a multiprocessor system.The main outcome of this project will be a deeper understanding on how the disruptive characteristics of Monolithic 3D integration can be exploited for improving the interconnect architecture in 3D integrated circuits. This allows for the design of optimized systems, not supported by current design concepts.