Balancing computations in in-memory nonvolatile heterogeneous systems

新兴的内存技术有可能破坏已经建立的冯-诺依曼计算范式。 特别是使用这些技术的近内存计算和内存计算，通过大大减少系统中的数据移动，有望在性能和能源效率方面实现前所未有的改进。 今天，有大量的手工优化的应用程序特定的近/内存系统的研究，源于计算架构社区。 这些系统中的大多数以单个底层存储器技术为特征，例如，在DRAM或PCM计算中，可能缺少竞争技术的功能和异构设置的协同效应。更广泛地采用这些新范式需要更一般和抽象的方式来推理不同底层内存技术所暴露的权衡。 同样，充分的软件抽象和新的编译方法是迫切需要的，以允许透明和有效地使用这种异构的新兴系统。 该项目研究了通用异构系统，集成了两种不同的内存计算（HetCIM）底层技术，即忆阻器件和基于自旋电子学的赛道。 前者已经被广泛研究用于加速线性代数运算（在深度神经网络中），而后者只是最近才扩展到支持批量逻辑运算。 从这些基本的计算原语及其相关的成本进行概括，将使我们能够设计一个高级编译框架，自动转换代码并将其映射到最佳匹配（CIM）技术。 为此，我们将建立一个多层次的编译管道，使用最近提出的MLIR框架，与设备特定的和设备无关的CIM中间表示。在这个级别上，我们将研究映射问题，以决定使用哪个设备进行哪些计算，并进行特定于设备的转换，例如，操作调度以延长忆阻器件的寿命或分摊赛道中的顺序访问等待时间。在更高的层次上，我们将利用特定于领域的抽象（例如，对于张量代数）沿着流行的仿射抽象（对于规则嵌套循环），并探索HetCIM系统的算法和多面体变换的空间。这些抽象将使我们能够展示编译框架，并评估HetCIM系统在机器学习，生物信息学和高性能计算领域的应用程序上的效率。

Emerging memory technologies have the potential to disrupt the established Von-Neumann computing paradigm. Near and in-memory computing with these technologies, in particular, promise an unprecedented improvement in performance and energy efficiency by greatly reducing data movement in the system. Today, there is a wealth of research on hand-optimized application-specific near/in-memory systems, stemming from the computing architecture community. Most of these systems feature a single underlying memory technology, e.g., in-DRAM or in-PCM computing, potentially missing on features from competing technologies and synergistic effects of heterogeneous setups. A broader adoption of these new paradigms requires more general and abstract ways of reasoning about the trade-offs exposed by different underlying memory technologies. Similarly, adequate software abstractions and novel compilation methodologies are badly needed to allow the transparent and efficient use of such heterogeneous emerging systems. This project studies generic heterogeneous systems integrating two different underlying technologies for computation in-memory (HetCIM), namely, memristive devices and spintronic-based racetracks. The former has been extensively studied for accelerating linear algebra operations (in deep neural networks), while the latter has only recently been extended with support for bulk logic operations. Generalizing from such fundamental computational primitives and their associated costs will allow us to devise a high-level compilation framework that automatically transforms code and maps it to the best-fit (CIM) technology. To this end, we will build a multi-level compilation pipeline, using the recently proposed MLIR framework, with device-specific and device-agnostic intermediate representations for CIM. At this level, we will study the mapping problem to decide which device to use for which computations and work on device-specific transformations, e.g., operation schedules to extend the lifetime of memristive devices or amortize the sequential access latency in racetracks. At higher levels, we will leverage domain-specific abstractions (e.g., for tensor algebra) along with the popular affine abstraction (for regular nested loops) and explore the space of algorithmic and polyhedral transformations for HetCIM systems. These abstractions will allow us to demonstrate the compilation framework and evaluate the efficiency of HetCIM systems on applications from the machine learning, the bioinformatics, and the high-performance computing domains.