Interferences in Design Methodology for High-performance Multi-Core Platforms

当系统对安全至关重要时，认证活动必须评估它是否符合该领域的适当标准。在InterMCore瞄准的航空电子和汽车领域，一个关键和开放的挑战是安全有效地使用异构高性能多核平台（例如，基于arm的带加速器的mpsoc），特别是在针对下一代应用时，混合不同的临界要求和执行模型。更准确地说，必须确定这些应用程序之间的干扰源，并对干扰进行量化，并可能减少干扰，以掌握系统的时间行为。虽然现有的工作通常集中在一个方面，如在最坏情况执行时间计算中识别时间异常或分析单个硬件组件引起的干扰，但显然缺乏一个综合（软件和硬件）方法感知流程，该流程可以解释干扰对复杂mpsoc的影响，以评估平台的可预测性并提供干扰缓解手段。InterMCore项目旨在通过以下方式构建这样一种以干扰为中心的方法：i)应用正式方法和基准测试来捕获mpsoc上这些应用程序的定时行为；ii)定义适当的规则和转换来指导应用程序软件合成，从编程模型到执行平台，以减少干扰，增强（即更可预测）定时行为。将开发一个全面的框架，用于评估和减轻在异构多核平台上执行的软件产生的干扰，这是有效设计下一代安全关键系统的一个关键特征。请注意，该提案已提交给ANR PRCI 2021电话会议，审稿人的意见已得到解决，特别是缩小了项目目标，并将重点从认证转移到拟议方法中的干扰（参见求职信以获得更详细的分析）。InterMCore项目结合了法国和德国合作伙伴的专业知识，用于：1)识别异构高性能mpsoc （ONERA）中的所有干扰源，2)使用应用程序负载和共享资源模型（TU Dortmund），根据最坏情况共享资源（通信和内存）延迟量化干扰的影响，3)在软件层面识别时间异常，并考虑硬件的形式化模型（CEA）和4)编程模型和编译技术，以实现更可预测的软件和硬件映射（TU Dresden）。该联盟将针对来自航空电子（法国方面）和汽车（德国方面）领域的不同类别的应用（例如控制和基于dnn的计算机视觉）。

When a system is safety-critical, a certification activity must evaluate whether it is compliant with the appropriate standards in that domain. In the avionic and automotive domains, targeted by InterMCore, a key and open challenge is the safe and efficient use of heterogeneous high performance multi-core platforms (e.g., ARM-based MPSoCs with accelerators), in particular when targeting next generation applications, mixing different criticality requirements and execution models. More precisely, the source of interferences between these applications must be identified and the interferences quantified and possibly reduced to master the temporal behavior of the system. While existing work often focuses on one aspect like identifying timing anomalies during the worst-case execution time computation or analyzing interferences caused by a single hardware component, there is a clear lack of a combined (software and hardware) methodology-aware flow which reasons about the effect of interference on complex MPSoCs to evaluate the predictability of the platform and provide means for interference mitigation. The InterMCore project aims at building such an interference-centric methodology by: i) applying both formal methods and benchmarking to capture the timing behavior of these applications over an MPSoCs and ii) defining appropriate rules and transformations to guide the application software synthesis, from the programming model down to the execution platform, for an enhanced (i.e., more predictable) timing behavior with reduced interferences. A comprehensive framework for assessing but also mitigating the interferences generated by software executed over heterogeneous multi-core platforms will be developed, a key feature for efficiently design the next generation of safety-critical systems. Note that this proposal was submitted to the ANR PRCI 2021 call and comments from reviewers have been addressed, in particular narrowing the goals of the project and move the focus from certification to interferences in the proposed methodology (see cover letter for a more detailed analysis). The InterMCore project combines expertise from French and German partners for: 1) identifying all sources of interference in heterogeneous high-performance MPSoCs (ONERA), 2) quantifying the effect of interference in terms of worst-case shared resources (communication and memory) delay using application loads and shared resources models (TU Dortmund), 3) identification of timing anomalies at the software level and considering formal models of the hardware (CEA) and 4) programming models and compilation techniques for a more predictable software and hardware mapping (TU Dresden). The consortium will target different classes of applications (e.g. control and DNN-based computer vision) from both the avionic (French side) and the automotive (German side) domains.