Interferences in Design Methodology for High-performance Multi-Core Platforms

当系统是安全关键型系统时，认证活动必须评估它是否符合该域中的适当标准。在InterMCore瞄准的航空电子和汽车领域，一个关键和开放的挑战是安全和高效地使用异类高性能多核平台(例如，带有加速器的基于ARM的MPSoC)，特别是在针对下一代应用、混合不同的关键要求和执行模型时。更准确地说，必须识别这些应用程序之间的干扰源，并量化并可能减少干扰，以掌握系统的时间行为。虽然现有的工作通常集中在一个方面，如在最坏情况下的执行时间计算期间识别定时异常或分析由单个硬件组件引起的干扰，但明显缺乏组合的(软件和硬件)方法感知流程，其原因是干扰对复杂MPSoC的影响，以评估平台的可预测性并提供干扰缓解的手段。InterMCore项目旨在通过以下方式构建这样一种以干扰为中心的方法：i)应用正式方法和基准来捕获MPSoC上这些应用程序的定时行为；ii)定义适当的规则和转换来指导应用软件合成，从编程模型到执行平台，以获得增强的(即，更可预测的)定时行为，同时减少干扰。将开发一个全面的框架，用于评估并减轻在不同类型的多核平台上执行的软件产生的干扰，这是有效设计下一代安全关键系统的关键特征。注意，这项提案已提交给ANR PRCI 2021年呼吁，审查员的意见也得到了处理，特别是缩小了项目目标，并将重点从认证转移到拟议方法的干预(更详细的分析见封面信)。InterMCore项目结合了法国和德国合作伙伴在以下方面的专业知识：1)确定异类高性能MPSoC(ONERA)中的所有干扰源；2)使用应用程序负载和共享资源模型(TU Dortmund)，根据最坏情况下的共享资源(通信和内存)延迟来量化干扰的影响；3)在软件层面确定时序异常，并考虑硬件的正式模型(CEA)；4)编程模型和编译技术，以实现更可预测的软硬件映射(TU Dresden)。该联盟将瞄准航空电子(法国一侧)和汽车(德国一侧)领域的不同类别的应用(例如，控制和基于DNN的计算机视觉)。

When a system is safety-critical, a certification activity must evaluate whether it is compliant with the appropriate standards in that domain. In the avionic and automotive domains, targeted by InterMCore, a key and open challenge is the safe and efficient use of heterogeneous high performance multi-core platforms (e.g., ARM-based MPSoCs with accelerators), in particular when targeting next generation applications, mixing different criticality requirements and execution models. More precisely, the source of interferences between these applications must be identified and the interferences quantified and possibly reduced to master the temporal behavior of the system. While existing work often focuses on one aspect like identifying timing anomalies during the worst-case execution time computation or analyzing interferences caused by a single hardware component, there is a clear lack of a combined (software and hardware) methodology-aware flow which reasons about the effect of interference on complex MPSoCs to evaluate the predictability of the platform and provide means for interference mitigation. The InterMCore project aims at building such an interference-centric methodology by: i) applying both formal methods and benchmarking to capture the timing behavior of these applications over an MPSoCs and ii) defining appropriate rules and transformations to guide the application software synthesis, from the programming model down to the execution platform, for an enhanced (i.e., more predictable) timing behavior with reduced interferences. A comprehensive framework for assessing but also mitigating the interferences generated by software executed over heterogeneous multi-core platforms will be developed, a key feature for efficiently design the next generation of safety-critical systems. Note that this proposal was submitted to the ANR PRCI 2021 call and comments from reviewers have been addressed, in particular narrowing the goals of the project and move the focus from certification to interferences in the proposed methodology (see cover letter for a more detailed analysis). The InterMCore project combines expertise from French and German partners for: 1) identifying all sources of interference in heterogeneous high-performance MPSoCs (ONERA), 2) quantifying the effect of interference in terms of worst-case shared resources (communication and memory) delay using application loads and shared resources models (TU Dortmund), 3) identification of timing anomalies at the software level and considering formal models of the hardware (CEA) and 4) programming models and compilation techniques for a more predictable software and hardware mapping (TU Dresden). The consortium will target different classes of applications (e.g. control and DNN-based computer vision) from both the avionic (French side) and the automotive (German side) domains.