INTEGRATION OF NEURAL NETWORKS USING SUPERCONDUCTIVE DEVICES

我们设计并制作了三种类型的约瑟夫森集成电路：一个基于神经元的3位A/D转换器、一个RS触发器电路和扩展的相模逻辑电路。该电路使用Nb/AlOx/Nb结工艺进行了集成，并使用低频模拟输入进行了测试。我们介绍了在APPL中的实验操作。太棒了。让我们来吧。和IEEE Trans。APPLRS触发器是为超导神经网络中的存储器件而设计的，由两个超导神经元器件和两个固定的突触电阻组成。数值模拟结果表明，它的高速工作频率高达50 GHz，这是我们在IEICE Transans中提出的。电子。实验结果已提交给IEEE Trans。APPL扩展相模逻辑(EPL)电路是为超导神经网络中的控制单元设计的。EPL电路使用单通量量子作为信息比特。抑制门的测试结果发表在IEEE Trans上，这是布尔代数中的通用运算之一。APPL超常行为。二进制计数器电路的测试结果已提交给IEICE Transans。电子。

We have designed and fabricated three types of Josephson integrated circuits ; a 3-bit neuron-based A/D converter, an RS flip-flop circuit, and extended phase-mode logic circuits.The 3-bit neuron-based A/D converter comprises three neuron devices and three synapse devices which we have developed recently. The circuit has been integrated using a Nb/ AlOx/Nb junction process and tested with low-frequency analog input. We have presented the experimental operation in Appl. Phys. Lett. and IEEE Trans. Appl. Superconduct.The RS flip-flop, which is designed for a memory device in superconducting neural networks, is composed of two superconducting neuron devices and two fixed synapse resistors. Numerical simulation results show its high speed operation up to 50GHz, which we have presented in IEICE Trans. Electron. Experimental results have been submitted to IEEE Trans. Appl. Superconduct.The extended phase-mode logic (EPL) circuits are designed for control units in superconducting neural networks. The EPL circuits utilizes a single-flux-quantum as an information bit. Test results for an INHIBIT gate, which is one of universal operations in terms of Boolean algebra, has been published in IEEE Trans. Appl. Superconduct. Test results for a binaly counter circuit has been submitted to IEICE Trans. Electron.