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Constitution of Neuro-based Dynamic Memory

Constitution of Neuro-based Dynamic Memory
基于神经的动态记忆的构成
批准号:
09450135
负责人:
NAKAJIMA Koji
金额:
$8.58万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1997
资助国家:
日本
项目状态:
已结题
起止时间:
1997 至 1999

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中文摘要
翻译
The purposes of this research are analyses for behaviors of neurobased dynamic memoriesresearch for applications of the memories, a constitution of the memoryanalyses for learning ability of the memoriesa hardware integration of the memories aimed at real time processings. We analyzed the number oflimit cycles generated in a single neural network by using a proposed learning algorithm. We alsoanalyzed the characteristics of the limit cycles and transition states to the limit cyclesand characteristics of a non-monotonic neuron network which has a higher performance of learningability. Interactions among the limit cycles, initial stateschaotic noise were investigated on fabricated neuro-chips with integrated chaotic signalgenerators. In order to investigate dynamic behaviors of quantized interconnection网络neuro-chips,我们已经设计和构建一个硬件neural network according to the design rule of a CMOStechnology. The 225 (and 42) full connections between 15 (and 7) neurons and The self-couplings canperformed in the fabricated neuro-chip. the number of limit cycles which can be produced on the单一network increases sharply with increasing the number of neurons in case of nearest neighborconnections. For an example,1.14x10 D17 D1 limit cycles in the case of 40 neurons are estimated at least. the limit cycleshave basins of attraction, and hence我们可以使用网络相关方法来重复动态循环模式。presented the quantized interconnection network to solve the N-parity problem and a random Booleanfunction with arbitrary N inputs. Finally,我们discussed the learning possibility for the quantized interconnection networks.这些results showneuro-based dynamic memories and the high possibility of applicationsof the memory as intelligent信息处理器。
英文摘要
The purposes of this research are analyses for behaviors of neuro-based dynamic memories, research for applications of the memories, a constitution of the memory, analyses for learning ability of the memories, a hardware integration of the memories aimed at real time processings. We analyzed the number of limit cycles generated in a single neural network by using a proposed learning algorithm. We also analyzed the characteristics of the limit cycles and transition states to the limit cycles, and characteristics of a non-monotonic neuron network which has a higher performance of learning ability. Interactions among the limit cycles, initial states, and chaotic noise were investigated on fabricated neuro-chips with integrated chaotic signal generators. In order to investigate dynamic behaviors of quantized interconnection networks on neuro-chips, we have designed and fabricated a hardware neural network according to the design rule of a CMOS technology. The 225 (and 42) full connections between 15 (and 7) neurons and the self-couplings can be performed in the fabricated neuro-chip. The number of limit cycles which can be produced on the single network increases sharply with increasing the number of neurons in case of nearest neighbor connections. For an example, 1.14x10ィイD17ィエD1 limit cycles in the case of 40 neurons are estimated at least. The limit cycles have basins of attraction, and hence, we may utilize the network as associative memeory to retrieve dynamical cyclic patterns. We also presented the quantized interconnection network to solve the N-parity problem and a random Boolean function with arbitrary N inputs. Finally, we discussed the learning possibility for the quantized interconnection networks. These results show the high performance of the neuro-based dynamic memories and the high possibility of applications of the memory as intelligent information processors.
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通讯作者:
H. Tanaka, S. Sato, and K. Nakajima: "Integrated Circuits of map Chaos Generators"IEICE Trans. Fundamentals. E82-A, 2. 364-369 (1999)
H. Tanaka、S. Sato 和 K. Nakajima:“地图混沌发生器的集成电路”IEICE Trans。
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Cheol-Young Park et al.: "Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles"IEICE Trans.on Fundamentals. E82-A. 952-957 (1999)
Cheol-Young Park 等人:“用于记忆极限环的量化互连神经网络的模拟 CMOS 实现”IEICE Trans.on 基础知识。
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