Development of Architectures and Design Methodologies of Customizable IP Cores for System-LSI's

本研究项目的目标是开发系统lsi的可定制IP核的架构和设计方法。本项目的研究成果如下：(1)开发可定制的IP核架构：该项目开发了几个可定制的处理器和协处理器作为可定制的IP核，以及这些IP核的设计方法。开发的技术包括(1)可定制处理器，其功能单元的性能和能耗可以在编译时或运行时（重新）配置和优化；(2)可定制的协处理器，其功能和组织可以在运行时重新配置；(3)在线硬件合成技术，为可定制的协处理器生成硬件配置信息，等等。(2)可定制存储核心架构开发：本项目已开发多个可定制存储核心及相关技术；(1)根据对指令位模式出现频率的统计分析，定制目标程序的指令解码，从而降低从程序ROM中获取指令所消耗的功耗；(2)根据指令获取地址的概况，定制和减少指令缓存的标签查找次数，从而降低检查指令缓存标签所消耗的功耗，等等。(3)开发可变大小数据路径和内存路径的定制技术：该项目开发了一些技术，用于分析源程序中变量的动态范围，然后确定数据路径和内存路径的大小，从而实现性能和功耗之间的权衡。

The objective of this research project is to develop architectures and design methodologies of customizable IP cores for system-LSI's. The project has performed the following research results.(1) Development of customizable IP core architectures : The project has developed several customizable processors and co-processors as customizable IP cores, and design methodologies for these IP cores. The technologies developed include (I) customizable processors where the performance and energy consumption of their functional units can be (re)configured and optimized at either compile time or run time, (ii)customizable co-processors whose functionality and organization can be reconfigured at run time, (iii) online hardware synthesis technology which produces hardware configuration information for the customizable co-processors, and so on.(2) Development of customizable memory core architectures : The project has developed several customizable memory cores and related technologies ; (I) customizing the instruction decoding for object programs, based on the statistical analysis on the appearance frequency of bit patterns of instructions, so that the power consumed for fetching instructions from a program ROM, (ii) customizing and reducing the number of tag lookups for instruction cache, based on the profile of instruction fetch addresses, so that the power consumed for checking the instruction cache tags, and so on.(3) Development of customization techniques for variable-size datapath and memory-path : The project has developed some techniques for analyzing the dynamic ranges of variables in source programs, and then determining the size of datapath and memory-path so that tradeoff between the performance and power consumption can be achieved.