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Thermal Deformation Analysis of Electronic Packages by Moire Interferometry and Phase-Shifting Method

Thermal Deformation Analysis of Electronic Packages by Moire Interferometry and Phase-Shifting Method
莫尔干涉和相移法对电子封装的热变形分析
批准号:
13650091
负责人:
ARAKAWA Kazuo
金额:
$2.3万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2001
资助国家:
日本
项目状态:
已结题
起止时间:
2001 至 2002

项目摘要

项目成果

ARAKAWA Kazuo的其他基金

相关文献

中文摘要
翻译
本文采用云纹干涉法对电子封装、四方平板封装(QFP)、多芯片组件(MCM)和倒装芯片(FC)的热变形进行了分析。还发展了高分辨率云纹干涉法来测量电子封装、SOJ(小轮廓J引线封装)和叠层MCP(多芯片封装)的热位移和应变。通过云纹干涉法测量QFP和MCM封装的热变形表明,芯片的边缘和拐角处发生了较大的变形。当QFP安装在印制线路板(PWB)上时,由于高热膨胀系数(CTE)基板的影响,变形增加。此外,还发现芯片数目和芯片在多芯片组件中的位置对封装变形有很大影响。对组件的热变形进行了评估,并对衬底和衬底的影响进行了…更多的调查。结果表明,底部填充在芯片和基板之间产生了类似的曲率。多层基板减少了芯片和基板之间的CTE失配和封装的弯曲变形。结果表明,在多层衬底上的封装中,焊球的热应变最小。发展了相移云纹干涉术和数字图像处理技术,并将其应用于纳米级位移分辨率的测量。数字图像处理使应变场的精确分析成为可能,相移法也被应用于SOJ和叠层MCP的热变形分析。两种封装的结果表明,切屑端部的法向应变较大,切屑拐角处的剪切应变较集中。当封装安装在印制板上时,SOJ的应变值增加了约50%。在叠层MCP中,法向应变也集中在两个芯片的界面处。当温度变化小于25℃时,下层切屑端部的剪切应变增加约76%
英文摘要
In the present research work, moire interferometry was applied to analyze thermal deformations of electronic packages, QFP (Quad Flat Package), MCM (Multi Chip Module) and FC (Flip-Chip Package). High-resolution moire interferometry was also developed to determine thermal displacements and strains of electronic packages, SOJ (Small Outline J-Leaded Package) and Stacked-MCP (Multi Chip Package). The conclusions from the present study can be summarized as follows.The thermal deformations of QFP and MCM packages measured by moire interferometry showed that high deformations occurred at the edges and corners of the chip. When the QFP was mounted on PWB (Printed Wiring Board), the deformations increased due to the influence of the substrate with high CTE (Coefficient of Thermal Expansion). It is also found that the number of chips and their locations in MCM greatly affected the package deformation.The thermal deformations of FCs were evaluated and the effects of underfill and substrate were … More investigated. The results showed that the underfill created similar curvatures between the chip and substrate. The multi-layer substrate decreased the CTE mismatch between the chip and substrate and the bending deformations of the packages. It is found that the thermal strains of solder balls were the smallest in the package underfilled and mounted on multi-layer substrate.Phase-shifting moire interferometry and digital image processing were developed and applied to nano-order resolution measurement in the displacements. The digital image processing made it possible to analyze the strain fields accurately.The phase-shifting method was also applied to the thermal deformation analyses of SOJ and Stacked-MCP. The results of the two packages showed that the normal strains were high at the ends of the chip, and the shear strain concentrated at the chip corners. The strain values in SOJ increased by about 50% when the package was mounted on PWB. In Stacked-MCP, the normal strain also concentrated at the interface of the two chips. The shear strain at the ends of the lower chip increased by about 76% with a temperature change of 25 deg.C. Less
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会议论文
森田康之, et al.: "電子デバイスの高温熱変形評価"日本機械学会講演論文集. NO.01-16. 139-140 (2001)
Yasuyuki Morita 等人:“电子器件高温热变形的评估”日本机械工程师学会会议记录 NO.01-16(2001)。
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通讯作者:
Y.Morita, et al.: "Thermal Deformation Analysis of Flip-Chip Packages by Moire Interferometry and FEA"Reports of Research Institute for Applied Mechanics. 121. 127-130 (2001)
Y.Morita等人:“通过莫尔干涉测量法和FEA对倒装芯片封装进行热变形分析”应用力学研究所的报告。
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通讯作者:
Y.Morita, et al.: "Thermal Strain Analysis of SOJ Electronic Package by Phase-shifting Moire Interferometry"Journal of JSEM. 3-1. 28-33 (2003)
Y.Morita 等人:“通过相移莫尔干涉测量法对 SOJ 电子封装进行热应变分析”JSEM 杂志。
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通讯作者:
Y.Morita, et al.: "Thermal Deformation Analysis of Flip-Chip Devices by Moire Interferometry"Journal of JIEP. 5-7. 654-659 (2002)
Y.Morita 等人:“通过莫尔干涉测量法对倒装芯片器件进行热变形分析”JIEP 杂志。
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