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Three Dimensional Dapapath Synthesis for Nanotechnology VLSIs

Three Dimensional Dapapath Synthesis for Nanotechnology VLSIs
纳米技术 VLSI 的三维 Dapapath 合成
批准号:
14550321
负责人:
KANEKO Mineo
金额:
$1.86万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2002
资助国家:
日本
项目状态:
已结题
起止时间:
2002 至 2003

项目摘要

项目成果

KANEKO Mineo的其他基金

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中文摘要
翻译
在纳米技术时代,互连延迟成为限制超大规模集成电路系统运行速度的主要因素,本研究旨在开发设计高性能超大规模集成电路系统的算法和软件系统。我们实现这一目标的关键方法是资源绑定、调度和平面图硬件模块的并发优化。我们的研究结果包括:1。绑定驱动调度:为了考虑数据路径合成期间的互连延迟,资源绑定(即,将操作分配给功能单元,将变量分配给寄存器)和平面图(即,每个模块在布局区域中的位置)必须先于调度。绑定驱动调度是为了解决给定资源绑定和平面图的时序分配问题而发展起来的。最小化互连数量的资源绑定:互连数量不仅影响硬件数量,还影响电路的电气性能。针对行为结构的局部相似性,提出了一种资源绑定算法,用于设计连接数较少的RTL体系结构。控制信号调度:提出了一种控制信号调度的设计算法,该算法可以在给定的数据路径部分的信号传输延迟和控制器到各模块的信号传输延迟下优化调度。在异步数字系统中的应用:针对异步数字系统的数据路径设计,对绑定驱动调度算法进行了改进,被认为是纳米技术时代有发展前景的技术之一。提出了一种表示三维数据路径解的编码系统,使传统的搜索方法如分支定界、局部搜索、模拟退火等可以适用于并发绑定、平面规划和调度问题。
英文摘要
The objective of this research is to develop algorithms and software systems to design high performance VLSI systems in nanotechnology era, where the interconnection delay becomes a dominant factor to limit the operation speed of VLSI systems. Our key approach to such objective is the concurrent optimization of resource binding, scheduling and floorplan hardware modules. Our results include the following.1.Binding driven scheduling : To consider interconnection delays during datapath synthesis, resource binding (i.e., assignment of operations to functional units, and variables to registers) and floorplan (i.e., location of each module in a layout area) must precede scheduling. Binding driven scheduling is so developed to solve timing assignment problem for a given resource binding and a floorplan.2.Resource binding for minimizing the number of interconnections : The number of interconnections affects not only the amount of hardware but also electrical performance of the circuit. Focusing on the local similarity of the behavioral structure, a resource binding algorithm has been developed for designing RTL architecture with a reduced number of interconnections.3.Control signal scheduling : An algorithm to design control signal schedule has been proposed, which can optimize the schedule under given signal transmission delay in datapath part and signal transmission delay from a controller to each module.4.Application to asynchronous digital systems : Our binding driven scheduling algorithm has been modified for datapath design of asynchronous digital system, which is considered as one of promising technologies in nanotechnology era.5.3-D datapath synthesis for reconfigurable systems : A coding system to represent solutions of 3-D datapath has been proposed, by which conventional searching method such as branch and bound, local search, simulated annealing, etc., can be applies to the concurrent binding, floorplan and scheduling problem.
期刊论文(24)
专著(0)
科研奖励(0)
会议论文
田湯智, 金子峰雄: "幅制約モジュール配置問題のSAを用いた最適化手法"電子情報通信学会技術報告. VLD2002-100. 109-114 (2002)
Satoshi Tayu、Mineo Kaneko:“使用 SA 解决宽度约束模块放置问题的优化方法”VLD2002-100 (2002)。
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Koji Ohashi, Mineo Kaneko: "Asynchronous Datapath Synthesis Based on Binding Space Exploration"電子情報通信学会回路とシステム軽井沢ワークショップ. (予定). (2004)
Koji Ohashi、Mineo Kaneko:“基于绑定空间探索的异步数据路径综合”IEICE 电路和系统轻井泽研讨会(计划)。
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厚見吉彦, 大橋功治, 金子峰雄: "計算アルゴリズムの局所的類似性とそのデータパス合成への応用"電子情報通信学会技術報告. (発表予定). (2003)
Yoshihiko Atsumi、Koji Ohashi、Mineo Kaneko:“计算算法的局部相似性及其在数据路径综合中的应用”IEICE 技术报告(待提交)。
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Post-Floorplan Control Schedule under Ma x/Min Logic/Interconnect Delays
最大/最小逻辑/互连延迟下的平面图后控制时间表
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发表时间: 2003
期刊: 電子情報通信学会第16回回路とシステム軽井沢ワークショップ論文集
影响因子: --
作者: [Mineo Kaneko, Koji Ohashi]
通讯作者: Koji Ohashi
共 23 条
    Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanism
    Theory and Optimization of Reliable Datapath Circuits having Robustness against Delay Variation
    Theory and Design Method of Clock-less Datapath for Next Generation VLSIs
    Theory and design of fault tolerant integrated systems
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