Energy Optimization for Asynchronous Circuits using Freedom of Execution Speed
Energy Optimization for Asynchronous Circuits using Freedom of Execution Speed
批准号:
21700062
负责人:
SAITO Hiroshi
金额:
$2.5万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Young Scientists (B)
财政年份:
2009
资助国家:
日本
项目状态:
已结题
起止时间:
2009 至 2011
中文摘要
在这项研究中,我们优化异步电路的能源消耗使用自由的执行速度。与所有操作的执行定时由全局时钟信号决定的同步电路不同,异步电路中的每个操作的执行定时可以自由决定。使用该自由度,执行能量优化。本研究的结果分为两个子结果。第一个是针对特定电路,第二个是针对处理器。针对具体电路,提出了一种能量优化方法。对于给定的行为描述的应用程序,延迟约束,和资源库,所提出的方法计算松弛为每个操作定义的开始时间在行为合成。然后,慢电路被分配给具有松弛的操作。在处理器方面,我们设计了一个适合FPGA和ASIC实现的异步AVR处理器。在能量优化方面,提出了面积优化和性能优化方法。与同步AVR处理器相比,异步AVR处理器的能耗仅为同步AVR处理器的一半。
英文摘要
In this research, we optimize asynchronous circuits in terms of energy consumption using freedom of execution speed. Different from synchronous circuits where execution timing of all operations is decided by a global clock signal, execution timing of each operation in asynchronous circuits can be decided freely. Using this freedom, energy optimization is carried out. The result of this research is classified into two sub result. The first is for specific circuits and the second is for processor. For specific circuits, we proposed an energy optimization method. For given behavioral description of an application, latency constraint, and resource library, the proposed method calculates slack for each operation defined for the start time during behavioral synthesis. Then, slow circuits are allocated to operations which have slack. For processor, we designed an asynchronous AVR processor aimed for FPGA and ASIC implementations. Also, for energy optimization, we proposed area optimization and performance optimization methods. Comparing to synchronous AVR processor, the energy consumption of our asynchronous AVR processor was half of the synchronous one.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
非同期式AVRプロセッサの設計
异步AVR处理器设计
DOI:
--
发表时间:
2011
期刊:
影响因子:
--
作者:
[六車英峰, 辻田祐一, 熊谷諒平]
通讯作者:
熊谷諒平
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