Study on architecture of high-performance computers

我研究了利用内存级并行（MLP）来抑制由于主存速度慢而导致的性能下降的计算机体系结构。MLP是将内存访问并行化。我提出了两个方案。一种是虚拟重排序缓冲器方案，其虚拟地增加处理器支持的指令的数量，并且通过抑制成本增加来促进MLP。另一种是动态指令窗口优化方案，其扩大支持大量指令的硬件，但自适应地调整硬件的大小以抑制由此产生的不利影响，即，时钟速度的降低和并行级开发的困难。我们的评估结果表明，虚拟重排序缓冲区和动态重排序计划实现的性能提高了35%和45%，分别比传统的处理器。

I studied computer architecture that exploits memory-levelparallelism (MLP) to suppress performance degradation due to slow main memory. MLP is to parallelize memory accesses. I proposed two schemes. One is a virtual reorder buffer scheme that virtually increases the number of instructions a processor supports, and promotes MLP with suppressing cost increase. Another is a dynamic instruction window resizing scheme that enlarges the hardware supporting a large number of instructions, but adaptively resizes the size of the hardware to suppress the adverse effect due to this, i.e., the degradation of the clock speed and difficulty of instruction-level parallelism exploitation. Our evaluation results show that the virtual reorder buffer and the dynamic resizing schemes achieve performance improvement by 35% and 45% over those of the conventional processor, respectively.