Research on high-performance microprocessor with distributed instruction-level parallelism

这项研究的目的是提出一种能够有效地利用整数程序的指令级并行的多处理器体系结构，并开发最佳利用该体系结构的编译器技术。本研究取得的成果如下。首先，我们提出了一种集成在单个芯片中的体系结构，该体系结构利用了来自多个线程的全局分布式指令级并行性。特别是，我们发现了一种机制，可以减少线程之间的通信和同步开销。此外，我们还改进了作为单处理器关键组件的分支预测器，并改进了双路径执行机制，以避免过度依赖分支预测。其次，我们为我们的体系结构开发了一个编译器，从而使采用我们提出的体系结构的计算机得到了广泛的应用。我们的编译器将顺序程序并行化并对其进行优化。我们的编译器的特点是在基本块级提取并行性，而不是传统编译器在循环级提取并行性。此外，我们还研究了程序中并行性的极限。通过我们的研究，我们证实了在基本块级别提取的并行度比在传统循环级别提取的并行度要大得多。我们还发现，我们的编译器的性能远远低于极限，留下了很大的改进空间。

The purposes of this study are to propose an architecture of a multi-processor that can efficiently exploit instruction-level parallelism for integer programs, and to develop compiler technologies that make the best use of that architecture. The achievements of this study are as follows. First, we have proposed an architecture integrated in a single chip that exploits globally distributed instruction-level rarallelism from multiple threads. Particularly, we have found a mechanism that can reduce the overhead of communication and synchronization among threads. Furthermore, we have improved branch predictors that are key components of a single processor, and have also improved both-path execution mechanisms to not excessively rely on branch prediction. Second, we have developed a compiler for our architecture so that the computer with our proposed architecture is widely used. Our compiler parallelizes a sequential program and optimizes it. The feature of our compiler is to extract parallelism at the basic block level unlike conventional compilers that extract parallelism at the loop level. Also, we have investigated the limit of parallelism in a program. From our investigation, we have confirmed that the amount of parallelism extracted at the basic block level is much larger than that extracted at the conventional loop level. We have also found that the performance of our compiler is much lower than the limit, leaving much room to improve.