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Research on high-performance microprocessor with distributed instruction-level parallelism

分布式指令级并行高性能微处理器的研究

基本信息

批准号：
10680348
负责人：
ANDO Hideki
金额：
$ 2.11万
依托单位：
Nagoya University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10680348/
关键词：
microprocessor multiprocessor instruction-level parallelism thread-level parallelism

项目摘要

The purposes of this study are to propose an architecture of a multi-processor that can efficiently exploit instruction-level parallelism for integer programs, and to develop compiler technologies that make the best use of that architecture. The achievements of this study are as follows. First, we have proposed an architecture integrated in a single chip that exploits globally distributed instruction-level rarallelism from multiple threads. Particularly, we have found a mechanism that can reduce the overhead of communication and synchronization among threads. Furthermore, we have improved branch predictors that are key components of a single processor, and have also improved both-path execution mechanisms to not excessively rely on branch prediction. Second, we have developed a compiler for our architecture so that the computer with our proposed architecture is widely used. Our compiler parallelizes a sequential program and optimizes it. The feature of our compiler is to extract parallelism at the basic block level unlike conventional compilers that extract parallelism at the loop level. Also, we have investigated the limit of parallelism in a program. From our investigation, we have confirmed that the amount of parallelism extracted at the basic block level is much larger than that extracted at the conventional loop level. We have also found that the performance of our compiler is much lower than the limit, leaving much room to improve.

本研究的目的是提出一个架构的多处理器，可以有效地利用整数程序的并行级，并开发编译器技术，使最好地利用该架构。本研究的主要成果如下。首先，我们提出了一种集成在单芯片中的架构，该架构利用多线程的全局分布式指令级rarallelism。特别是，我们发现了一种机制，可以减少线程之间的通信和同步的开销。此外，我们改进了分支预测器，这是一个单一的处理器的关键组件，也改善了双路径执行机制，不过分依赖于分支预测。其次，我们已经开发了一个编译器，我们的架构，使我们提出的架构的计算机被广泛使用。我们的编译器并行化一个顺序的程序，并优化它。我们的编译器的特点是提取并行在基本块级别不同于传统的编译器，提取并行在循环级别。此外，我们还研究了程序中并行性的极限。从我们的调查中，我们已经证实，在基本块级提取的并行量远远大于在传统的循环级提取。我们还发现，我们的编译器的性能远远低于限制，留下了很大的空间，以提高。