Study on architectures of high-performance computers

本研究提出一种数据预取方案，以抑制因主存速度慢而导致的性能下降。在这里，预取在处理器需要数据之前将数据从主存移动到缓存中。尽管已经进行了许多研究，但它们仅在像数组访问这样的常规模式下是成功的，这是高度可预测的。另一方面，本研究提出了一种通用的预取方案，该方案可以成功地处理各种数据访问模式，包括不规则模式。

This study proposed a data prefetch scheme that suppresses performance degradation due to slow main memory. Here, prefetching moves data from main memory to a cache before a processor requires them. Although many studies have been carried out, they are successful only for regular patterns like array accesses, which are highly predictable. On the other hand, this study proposed a general prefetch scheme, which allows to successfully handle various data access patters including irregular patterns.