Variation-Adaptive Design in FPGAs

该建议涉及深亚微米可配置数字电路中的参数变化补偿设计技术。过去四十年来，微电子行业的增长一直基于减小晶体管的尺寸，使集成电路更小，更快，更便宜。晶体管缩放所获得的好处正在减少，因为它变得越来越难以控制的参数在一个单一chip.The研究建议将探讨新的变化感知设计技术在深亚微米可编程逻辑器件的传播。这与最近开发的微电子公司的“路线图，特别是GC 3-摩尔更少”是一致的。研究的前提是，一个单一的设计可以在一个给定的可编程逻辑器件中以多种方式实现。在变化的存在下，不同的实现将表现出不同的性能，虽然它们是功能相同的。目的是发现和开发策略，利用现有的可编程逻辑器件中的这一功能。此外，将提出对此类装置的结构修改以增加可获得的益处。这些目标将实现从一个彻底的分析的性质参数变化的实证研究，其次是严格使用概率建模和优化理论。

This proposal is concerned with design techniques to compensate for parametric variations in deep-submicron configurable digital circuits. The growth of the microelectronics industry over the last four decades has been based on reducing the size of transistors to make integrated circuits smaller, faster and less expensive. The benefits obtained by transistor scaling are now diminishing as it becomes increasingly difficult to control the spread of parameters within a single chip.The research in this proposal will investigate new variation-aware design techniques in deep-submicron programmable logic devices. This is well-aligned with the recently developed Microelectronics Grand Challenges'' roadmap, particularly GC3---Moore for Less''. The premise for the research is that a single design can be implemented in more than one way in a given programmable logic device. In the presence of variations, distinct implementations will exhibit different performances, although they are functionally identical.The intention is to discover and develop strategies which exploit this feature in existing programmable logic devices. Furthermore, architectural modifications to such devices will be proposed to increase the obtainable benefit. These goals will be achieved from a thorough analysis of the nature of parametric variability from empirical studies, followed by the rigorous use of probabilistic modelling and optimisation theory.