PAnDA: Programmable Analogue and Digital Array

摩尔定律指出，自1947年发明晶体管以来，集成电路上的晶体管数量每两年翻一番。这是由于技术的进步导致设备的缩小。然而，随着这些设备接近原子水平，内在变化变得越来越多，导致较低的产量和较高的故障率。为了适应单个器件特性的增加可变性，需要新的器件体系结构和电路设计方法。例如，为了达到45纳米CMOS技术节点，英特尔被迫对晶体管技术进行了自20世纪60年代以来最大的变革。这些预测和问题最初集中在大规模集成上，主要与微处理器设计有关。然而，在过去的10年里，现场可编程设备（例如现场可编程门阵列- FPGA）在技术进步和应用领域方面的兴起意味着这些问题现在也与这些设备相关。因此，该提案侧重于当前电子设计中最大的挑战之一：当器件尺寸缩小到原子水平时，考虑到内在可变性的物理效应，以实现功能电路设计。工艺和衬底的变化都对这种小型器件的可靠制造提出了重大挑战。这些变化可分为两类；确定性可变性可以使用特定的设计技术精确建模和解释，而随机可变性只能通过统计建模，而且很难克服。该提案将开发一个可重构的设计平台，可以在设备和数字抽象层面进行操作，以便进一步理解和解决硬件随机变异性对下一代设计的影响。该研究计划包括四个相互建立的线程：-设计一个可变性容忍架构的仿真模型，-该模型的硬件实现，-开发一个全面的软件框架，它将能够连接仿真模型和芯片，-开发生物启发的方法来解决可变性容忍设计。最后，该项目将对随机变异性如何影响未来的电路设计有一个了解，并将提出新的设计方法来克服随机变异性。一个新颖的，可变性容忍架构将被开发和实现作为一个仿真模型和硬件的原型。两者都是迈向下一代FPGA架构的重要步骤。

Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.