SIPP - Secure IoT Processor Platform with Remote Attestation

随着世界变得越来越紧密，大量的物联网（IoT）设备需要使用智能、自主的机器对机器通信；然而，这带来了严重的安全和隐私问题，因为我们将不再直接控制我们的设备与什么或谁通信。假冒、被黑客攻击或克隆的设备在网络上运行可能会产生重大后果：对于个人来说，通过泄露机密和个人信息，在货币成本方面（例如，失去对网络服务的访问- Mirai对Dyn的攻击导致Twitter、Spotify、Reddit关闭）；或者对于关键的国家基础设施，通过失去对安全至关重要的工业和网络物理物联网系统的控制。此外，物联网设备通常是低成本、低功耗的设备，在内存和计算能力方面都受到限制。一个主要的挑战是如何解决这种资源受限设备的安全需求。随着公司竞相将物联网设备推向市场，许多公司没有考虑安全性，或者往往是事后才考虑安全性。因此，物联网所有领域的一个共同主题是对可靠性和安全性的需求。SIPP项目旨在重新思考如何将安全性构建到物联网处理器平台中。首先，处理器设计的架构基础需要重新设计，以确保单个片上组件的安全性。这在最近的Spectre和Meltdown攻击中变得越来越明显。在片上系统（soc）的上层，对芯片子系统和整个芯片的硬件认证是检测恶意硬件修改的关键。然后，在系统层（即在普通印刷电路板上的多个芯片），将研究用于远程认证的创新方法，以确定板级的完整性。最后，将通过调查物理层漏洞来评估所有分层层实现的安全性，以确保每一层所依赖的秘密没有物理泄漏。拟议的项目汇集了NCSC/ epsrc资助的安全硬件和嵌入式系统研究所（RISE）的核心合作伙伴，即贝尔法斯特女王大学、剑桥大学、布里斯托尔大学和伯明翰大学，以及新加坡国立大学和南洋理工大学在硬件安全和安全架构设计领域的领先学者。开发一种在RISC-V架构上实现远程认证的新型安全物联网处理器平台。

As the world becomes ever more connected, the vast number of Internet of things (IoT) devices necessitates the use of smart, autonomous machine-to-machine communications; however, this poses serious security and privacy issues as we will no longer have direct control over with what or whom our devices communicate. Counterfeit, hacked, or cloned devices acting on a network can have significant consequences: for individuals through the leakage of confidential and personal information, in terms of monetary costs (for e.g. the loss of access to web services - Mirai attack on Dyn took down Twitter, Spotify, Reddit); or for critical national infrastructure, through the loss of control of safety-critical industrial and cyber-physical IoT systems. In addition, IoT devices are often low-cost, low power devices that are restricted in both memory and computing power. A major challenge is how to address the need for security in such resource-constrained devices. As companies race to get IoT devices to market, many do not consider security or, all too often, security is an afterthought. As such, a common theme in all realms of IoT is the need for dependability and security. The SIPP project aims to rethink how security is built into IoT processor platforms. Firstly, the architectural fundamentals of a processor design need to be re-engineered to assure the security of individual on-chip components. This has become increasingly evident with the recent Spectre and Meltdown attacks. On the upper layer of systems-on-chip (SoCs), hardware authentication of chip sub-systems and the entire chip is crucial to detect malicious hardware modification. Then, at the systems layer (i.e., multiple chips on a common printed circuit board), innovative approaches for remote attestation will be investigated to determine the integrity at board level. Finally, the security achieved at all hierarchical layers will be assessed by investigating physical-level vulnerabilities to ensure there is no physical leakage of the secrets on which each layer relies. The proposed project brings together the core partners of the NCSC/EPSRC-funded Research Institute in Secure Hardware and Embedded Systems (RISE), that is, Queen's University Belfast and the Universities of Cambridge, Bristol and Birmingham, with the leading academics in the field of hardware security and security architecture design from the National University of Singapore and Nanyang Technological University, to develop a novel secure IoT processor platform with remote attestation implemented on the RISC-V architecture.