Perovskite X-ray Photon Counting Detector

钙钛矿X射线光子计数探测器(PePAD)项目致力于通过将高质量的钙钛矿(PVK)单晶直接生长到像素化专用集成电路(ASIC)阵列上来开发多像素化光子计数探测器(PCD)，从而实现第一个像素化PVK基PCD。PePAD是一个由以下目标组成的雄心勃勃的项目。目标1：在与器件相关的衬底上模块化和形状控制生长PVK单晶，其光电性能与传统的碲化镉(CdTe)或碲化锌镉(CZT)半导体相当。WP1将首先允许通过逆温结晶(ITC)方法制造PVK单晶。优化PVK单晶生长的手段将包括调节A位阳离子(FA、Cs和/或MA)的分数，以及在晶体生长中使用包括EDTA在内的添加剂，这是受到主办组最近的工作的启发。目标2：制造并建立对单像素PCD的强大的基础理解，该单像素PCD具有自操作能力(在0V外加偏压)、低暗电流、高能量分辨率和稳定的运行。WP2将允许优化设备架构及其组件。单像素PCD的一般结构将是Me/HTL/PVK单晶/ETL/Me或TCO。将对界面进行优化，以最好地解决PVK和ETL或HTL界面上出现的缺陷，包括使用2D/3D表面、LiF和/或受光伏工作启发的MgF2薄层。目标3：制造和演示高性能像素化PCD，具有低电荷共享和低像素间泄漏电流，在特定通量和高图像分辨率下没有脉冲堆积效应。WP3将允许直接在ASIC阵列上演示已经在WP1中优化的PVK单晶生长。将WP2中优化的电荷传输层和电极沉积在PVK单晶上，完成多像素PCD。

Perovskite X-ray Photon Counting Detectors (PePAD) project focuses on the development of multi-pixelated photon counting detectors (PCDs) via growing high-quality perovskite (PVK) single crystals directly onto pixelated application-specific integrated circuit (ASIC) arrays, thus realising the first pixelated PVK-based PCDs. The PePAD is an ambitious project comprised of the following objectives.Objective 1: Modular and shape-controlled growth of PVK single crystals onto device-relevant substrates with optoelectronic properties rivalling to conventional Cadmium Telluride (CdTe) or Cadmium Zinc Telluride (CZT) semiconductors. WP1 will first allow fabricating PVK single crystals via inverse temperature crystallisation (ITC) method. The levers to optimise the PVK single crystals growth will include tuning fractions of A-site cations (FA, Cs and/or MA) and additives in the crystal growth including EDTA will be used inspired by the host group's recent work.Objective 2: Fabrication and build a strong fundamental understanding of single-pixel PCD with self-operating capability (at 0V applied bias), low dark current, high energy resolution and stable operation. WP2 will allow optimisation of device architecture and their components. The general structure of single-pixel PCD will be a Me/HTL/PVK single crystal/ETL/Me or TCO. Interfaces will be optimised to best address the defects arising at the interfaces of PVK and ETL or HTL, including use of 2D/3D surfaces, LiF and/or MgF2 thin layers inspired by PV works.Objective 3: Fabrication and demonstration of high-performance pixelated PCD with low charge sharing and low pixel-to-pixel leakage current, without pulse pileup effect at certain fluxes and high image resolution. WP3 will allow demonstration of PVK single crystal growth already optimised in WP1 directly on the ASIC arrays. The optimized charge transport layers and electrodes in WP2 will be deposited on the PVK single crystals to complete multi-pixel PCDs.