Communication Centric Microelectronic Design

我们希望对通信中心的微电子设计方法进行研究，这些方法与当今以计算为中心(或门级)的技术形成对比。我们相信这项研究是及时的，因为电子学正处于变革的边缘。在过去的60年里，数字门的生产成本一直很高，而且性能有限。我们现在正在进入一个曾经几乎免费的电线时代，它成为了成本和性能的界限。这一趋势在国际半导体技术路线图(ITRS)路线图中得到了很好的记录，该路线图清楚地确定了电路和相关设计技术所需的阶跃变化。他们还发现了螺旋式上升的设计复杂性、不断上升的功率密度和相关的热问题。我们相信，片上网络解决了未来纳米CMOS实现技术的许多设计挑战。背景我们在这方面的研究已经产生了一种低延迟的片上网络体系结构，该体系结构是我们在180 nm的CMOS上制作的。这项初步工作集中在我们与麻省理工学院开发的平铺处理器体系结构之间的互连。然而，对于这个项目，我们希望走得更远，着眼于多个层次的通信和一系列技术，从芯片上的ASIC设计到新的现场可编程门阵列(FPGA)架构。现场可编程门阵列架构与我们通常的研究方向不同，因此我们特别荣幸地从Altera UK(两家大型国际现场可编程门阵列公司之一)获得了全额资助的博士生奖学金，他们将在这个项目上与我们合作。

We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.