Application of error-control codes to digital systems testing

基于可编程逻辑器件（pld）的可重构计算平台（rcp）已广泛应用于航空航天、柔性制造、无线通信等各个领域。使用这种方法的主要原因是这种rcp能够使其硬件适应应用程序的算法和数据结构。与传统的基于微处理器的平台相比，这一重要特性确保了高性价比。当今应用的复杂性不断提高，使得基于SRAM的现场可编程门阵列（FPGA）成为PLD最合适的选择。然而，这种fpga非常容易受到辐射和其他环境因素的影响。随着VLSI特征尺寸的减小，易感性倾向于增加，抑制了基于SRAM FPGA的rcp在核电站、航空航天和军事领域的使用，这些领域对rcp的要求最高。提出的研究的主要目的是开发面向数字器件的测试方法，这将适用于基于SRAM FPGA的rcp，并将提高其容错性。为实现这一目标，将完成下列任务：-将审查错误控制码（ECC）在数字设备在线测试中的适用性-将分析简单硬件实现的编码/解码算法和编码器/解码器-将检查基于最有效ECC的自检和离线数字测试方法-将审查基于ECC的测试方法对部分可重构fpga（例如Xilinx Virtex系列）的适用性-硬件恢复程序基于将研究fpga中数据处理微架构的重新定位（可能会导致性能下降）。研究的结果将是发明新的在线和离线数字测试方法，这将有助于开发具有改进寿命参数的高性能可靠RCP。

Reconfigurable Computing Platforms (RCPs) based on programmable logic devices (PLDs) have been widely used in various areas: aerospace, flexible manufacturing, wireless communication, etc. The primary reason for this use is the ability of such RCPs to adapt their hardware to the algorithm and data structure of the application. This important feature ensures high cost-performance characteristics compared to conventional microprocessor based platforms. Increasing level of complexity of nowadays applications has made an SRAM based Field Programmable Gate Array (FPGA) the most suitable choice for a PLD. However, such FPGAs are highly susceptible to radiation and other environmental factors. With reduction of a VLSI feature size the susceptibility tends to increase inhibiting the use of SRAM FPGA based RCPs in nuclear power stations, aerospace, and military areas, which are the most demanding for RCPs. The main objective of the proposed research is to develop testing methods oriented to digital devices, which will be applicable to SRAM FPGA based RCPs and will increase their fault tolerance. To achieve this objective the following tasks will be accomplished: - Error-Control Codes (ECC) will be reviewed in terms of applicability to on-line testing of digital devices - Encoding/decoding algorithms and encoder/decoders with simple hardware implementation will be analyzed - Self-checking as well as off-line digital testing methods based on the most efficient ECC will be examined - Applicability of the testing methods based on the ECC to partially reconfigurable FPGAs (e.g. Xilinx Virtex family) will be scrutinized - Hardware recovery procedures based on relocation of data-processing micro-architectures in FPGAs (with possible performance degradation) will be investigated. The outcome of the research will be invention of new on-line and off-line digital testing methods, which will contribute to development of a high-performance dependable RCP with improved lifetime parameters.