Interconnects aware design methodology for high-performance nanometer CMOS circuits

随着技术规模的缩小，芯片上的晶体管数量急剧增加，如半导体行业协会路线图预测的那样，65纳米技术的晶体管数量达到2.5亿个。这导致互连长度、密度和复杂性增加。随着工作频率的提高，互连线对延迟、功耗、带宽和噪声等设计性能的影响越来越难以忽视。尽管铜和低介电常数绝缘体等材料发生了重大变化，但这种效应已将性能影响因素从栅极转移到互连。拟议的研究工作的重点是研究互连在确定当前和未来几代CMOS高速IC的性能方面发挥的日益重要的作用。研究人员将使用这些结果来开发高性能纳米CMOS电路的互连感知设计方法。这种方法将减少周转时间，实现快速的时序收敛，这是非常重要的，以降低设计成本，缩短上市时间。

With technology down scaling, the number of transistors on-chip has increased dramatically and reached up to 250 million transistors in 65nm technology as predicted by Semiconductor Industry Association Roadmap. This caused interconnect lengths, density and complexity to increase. Combined with higher operating frequency it has become increasingly difficult to ignore the effect of interconnects on the design performance such as delay, power, bandwidth, and noise. This effect has shifted the performance influential factors from gates to interconnect despite major changes in materials such as copper and low-dielectric-constant insulators. The focus of the proposed research work is to study the increasingly important role interconnects play in determining the performance of the current and future generations of CMOS high-speed ICs. The investigator will use these results to develop interconnect aware design methodology for high-performance nanometer CMOS circuits. This methodology will reduce the turn around time and achieve fast timing closure, which is very important to lower the design cost and shorten time-to-market.