Frontiers-based synthesis of digital logic

硬件描述语言(Hardware Description Languages，HDL语言)一直停留在较低的语义层，抽象能力有限。但这些特点使得VLSI ASIC和FPGA的开发本身就更加困难和昂贵。程序设计语言及其语义的研究已经建立了一条向语义更清晰、抽象能力更强的规范/实现语言发展的道路。众所周知，这种语言可以改善硬件描述、综合和验证的过程。但是，由于缺乏一种方法来弥合功能更强大的语言和布尔门之间的巨大语义鸿沟，阻碍了这一方向的实际进展。然而，由于缺乏一种方法来弥合功能更强大的语言和布尔门之间的巨大语义鸿沟，因此阻碍了这方面的实际进展申请人和一位博士生的工作建立了一种从这些抽象语言综合最小门实现的有效方法。该方法基于扩展布尔域中的边界计算。建议的工作将：a)改进早期工作的理论基础，b)使规范语言更加丰富并支持综合器中的新功能，c)将该规范语言嵌入到Verilog中，以便可以在实验中使用完整的Verilog工具链，以及d)从长远来看，将该语言扩展到VLSI社区迟早必须接受的异步设计领域。

Hardware description languages (HDL) have remained at a low semantic level, and have limited abstraction capabilities.  These characteristics make the development of VLSI ASICs and FPGAs inherently more difficult and expensive.  Research in programming languages and their semantics has established a path toward specification/implementation languages which have much cleaner semantics and strong powers of abstraction.  It has been known that such languages could improve the processes of hardware description, synthesis, and verification.  But the lack of a method of bridging the large semantic gap between the more powerful languages and Boolean gates has prevented practical progress in this direction.  However, work by the applicant and a former PhD student has established an efficient means of synthesizing minimal gate implementations from these abstract languages.  This method is based on the computation of frontiers in extended Boolean domains.  The proposed work will: a) improve the theoretical basis of the earlier work, b) make the specification language richer and support the new features in the synthesizer, c) embed this specification langauge in Verilog, such that a full Verilog tool chain can be used in experiments, and d) in the longer term, extend this language into the asynchronous design domain which the VLSI community must sooner or later embrace.